公开(公告)号：US06878961B2

公开(公告)日：2005-04-12

申请号：US10951370

申请日：2004-09-28

申请人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Mark S. Chang

发明人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Mark S. Chang

IPC分类号： G11C11/56 ,  G11C13/02 ,  H01L27/28 ,  H01L35/24

CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/025 ,  G11C13/04 ,  Y10S977/943

摘要： A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer is formed into memory cells using patterning techniques.

摘要翻译： 公开了一种由在两个电极之间具有可控导电介质的两个电极制成的有机存储单元的方法。 可控导电介质包含含有光敏化合物的有机半导体层。 使用图案化技术将有机半导体层形成为存储单元。

公开(公告)号：US06864024B1

公开(公告)日：2005-03-08

申请号：US10302225

申请日：2002-11-22

申请人： Christopher F. Lyons ,  Bharath Rangarajan

发明人： Christopher F. Lyons ,  Bharath Rangarajan

IPC分类号： A61N5/00 ,  G03C5/00 ,  G03F7/038 ,  G03F7/039 ,  G03F9/00

CPC分类号： G03F7/0382 ,  G03F7/0392

摘要： One aspect of the present invention relates to a system and method for controlling environmental acid scavengers in real time during pattern exposure of a chemically amplified resist-clad wafer. The system includes a semiconductor wafer comprising a chemically amplified resist layer formed over a substrate layer, wherein a first portion of the resist layer has been removed to expose an area of the substrate layer in order to form a probe area; an exposure system programmed to implement an exposure process to transfer a device pattern onto at least a second portion of the resist layer; and a monitoring system adapted to detect chemical signals about the probe area in order to control the integrity of the resist layer during the exposure process. The method involves feeding data back to the on-going exposure process in order to effect an immediate change in the process.

摘要翻译： 本发明的一个方面涉及在化学放大的抗蚀剂包覆晶片的图案曝光期间实时控制环境酸清除剂的系统和方法。 该系统包括半导体晶片，其包括在衬底层上形成的化学放大抗蚀剂层，其中已除去抗蚀剂层的第一部分以暴露衬底层的区域以形成探针区域; 曝光系统被编程为实现曝光过程以将装置图案转印到抗蚀剂层的至少第二部分上; 以及适于检测关于探针区域的化学信号以便在曝光过程期间控制抗蚀剂层的完整性的监测系统。 该方法涉及将数据馈送回正在进行的曝光过程，以便立即改变过程。

公开(公告)号：US06849530B2

公开(公告)日：2005-02-01

申请号：US10334337

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

IPC分类号： H01L21/28 ,  H01L21/4763

CPC分类号： H01L21/28123

摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

公开(公告)号：US06829040B1

公开(公告)日：2004-12-07

申请号：US10703643

申请日：2003-11-07

申请人： Jongwook Kye ,  Ivan Lalovic ,  Christopher F. Lyons ,  Ramkumar Subramanian

发明人： Jongwook Kye ,  Ivan Lalovic ,  Christopher F. Lyons ,  Ramkumar Subramanian

IPC分类号： G03B2742

CPC分类号： G03F7/70575 ,  G03F7/703 ,  G03F7/70333

摘要： A projection lithography system exposes a photo sensitive material on a surface of a semiconductor substrate that includes surface height variations between a high level and a low level. The system comprises an illumination source projecting illumination within a narrow wavelength band centered about a nominal wavelength on an optic path towards the substrate during an exposure period. A wavelength modulation system within the optic path comprises means for chromatically separating the narrow wavelength band into at least two sub-bands, the first sub-band being smaller than the narrow wavelength band and centered about a first sub-band wavelength and the second sub-band being smaller than the narrow wavelength band and centered about a second sub-band wavelength and means for passing each of the first sub-band and the second sub-band during distinct time periods within the exposure period.

摘要翻译： 投影光刻系统在半导体衬底的表面上曝光感光材料，其包括高电平和低电平之间的表面高度变化。 该系统包括照射源，其在曝光期间内以在光路上朝着衬底的标称波长为中心的窄波长带内投射照明。 光路内的波长调制系统包括用于将窄波段色带分离成至少两个子带的装置，第一子带小于窄波段并以第一子带波长为中心，第二子带 带窄于窄波长带并以第二子带波长为中心，以及用于在曝光周期内的不同时间段内通过第一子带和第二子带中的每一个的装置。

公开(公告)号：US06787458B1

公开(公告)日：2004-09-07

申请号：US10614397

申请日：2003-07-07

申请人： Nicholas H. Tripsas ,  Matthew S. Buynoski ,  Suzette K. Pangrle ,  Uzodinma Okoroanyanwu ,  Angela T. Hui ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Ashok M. Khathuria ,  Mark S. Chang ,  Patrick K. Cheung ,  Jane V. Oglesby

发明人： Nicholas H. Tripsas ,  Matthew S. Buynoski ,  Suzette K. Pangrle ,  Uzodinma Okoroanyanwu ,  Angela T. Hui ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Ashok M. Khathuria ,  Mark S. Chang ,  Patrick K. Cheung ,  Jane V. Oglesby

IPC分类号： H01L2144

CPC分类号： H01L27/285 ,  H01L2924/0002 ,  H01L2924/00

摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.

摘要翻译： 本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。 该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔 露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

公开(公告)号：US06773998B1

公开(公告)日：2004-08-10

申请号：US10445129

申请日：2003-05-20

申请人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21336

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/3146 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.

摘要翻译： 集成电路的方法包括使用无定形碳ARC掩模。 一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。 蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。 然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

公开(公告)号：US06654660B1

公开(公告)日：2003-11-25

申请号：US10287292

申请日：2002-11-04

申请人： Bhanwar Singh ,  Christopher F. Lyons ,  Bharath Rangarajan ,  Khoi A. Phan ,  Ramkumar Subramanian

发明人： Bhanwar Singh ,  Christopher F. Lyons ,  Bharath Rangarajan ,  Khoi A. Phan ,  Ramkumar Subramanian

IPC分类号： G06F1900

CPC分类号： G03F7/70425 ,  G03F7/70875

摘要： One aspect of the present invention relates to a system and method for controlling thermal expansion on an EUV mask during EUV photolithography. The system includes an EUV photolithography system for irradiating one or more layers of a wafer through one or more gratings of a patterned EUV mask, whereby heat accumulates on at least a portion of the patterned EUV mask during the irradiation of the one or more layers of the wafer; an EUV mask inspection system for monitoring the one or more gratings on the mask to detect expansion therein, the inspection system producing data relating to the mask; and a temperature control system operatively coupled to the inspection system for making adjustments to the EUV photolithography system in order to compensate for the detected expansion on the mask. The method involves employing feedback and feed forward control to optimize the current and future EUV photolithography processes.

摘要翻译： 本发明的一个方面涉及一种用于在EUV光刻期间控制EUV掩模上的热膨胀的系统和方法。 该系统包括用于通过图案化的EUV掩模的一个或多个光栅照射晶片的一个或多个层的EUV光刻系统，由此在图案化的EUV掩模的照射期间在图案化的EUV掩模的至少一部分上积聚热量 晶圆; 用于监视所述掩模上的所述一个或多个光栅以检测其中的扩展的EUV掩模检查系统，所述检查系统产生与所述掩模有关的数据; 以及温度控制系统，其可操作地耦合到所述检查系统，以对EUV光刻系统进行调整，以便补偿所述掩模上检测到的膨胀。 该方法涉及采用反馈和前馈控制来优化当前和未来的EUV光刻工艺。

公开(公告)号：US06635409B1

公开(公告)日：2003-10-21

申请号：US09902568

申请日：2001-07-12

申请人： Christopher F. Lyons ,  Scott A. Bell ,  Todd Lukanc ,  Marina V. Plat

发明人： Christopher F. Lyons ,  Scott A. Bell ,  Todd Lukanc ,  Marina V. Plat

IPC分类号： G03F700

CPC分类号： G03F7/40 ,  G03F7/2024

摘要： There is provided a method for forming a photoresist layer for photolithographic applications which has increased structural strength. The photoresist layer is exposed through a mask and developed. The photoresist layer is then treated to change its material properties before the photoresist layer is dried. Also provided are a semiconductor fabrication method employing a treated photoresist and a composition for a treatable photoresist.

摘要翻译： 提供了一种形成光刻应用的光致抗蚀剂层的方法，其具有增加的结构强度。 光致抗蚀剂层通过掩模曝光并显影。 然后在光致抗蚀剂层干燥之前，处理光致抗蚀剂层以改变其材料性质。 还提供了使用经处理的光致抗蚀剂和用于可处理光致抗蚀剂的组合物的半导体制造方法。

公开(公告)号：US06599810B1

公开(公告)日：2003-07-29

申请号：US09186078

申请日：1998-11-05

申请人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

发明人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

IPC分类号： H01L2176

CPC分类号： H01L21/76237 ,  H01L21/26586 ,  H01L21/76235

摘要： An insulated trench isolation structure is formed by ion implanting impurities proximate to the trench edges for enhancing the oxidation rate and, hence, increasing the thickness of the oxide at the trench edges. Embodiments include ion implanting impurities prior to growing an oxide liner. The resulting thick oxide on the trench edges avoids overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.

摘要翻译： 通过离子注入靠近沟槽边缘的杂质形成绝缘沟槽隔离结构，以增强氧化速率，并因此增加沟槽边缘处氧化物的厚度。 实施例包括在生长氧化物衬垫之前的离子注入杂质。 沟槽边缘上产生的厚氧化物避免随后沉积的多晶硅层的重叠以及伴随沟槽边缘处的薄化栅极氧化物的破坏问题。

公开(公告)号：US06558965B1

公开(公告)日：2003-05-06

申请号：US09901702

申请日：2001-07-11

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Christopher F. Lyons ,  Marina V. Plat

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Christopher F. Lyons ,  Marina V. Plat

IPC分类号： H01L2166

CPC分类号： G03F7/091 ,  G01B11/0616 ,  H01L21/0276

摘要： A method of forming a semiconductor device is described. A bottom anti-reflective coating (BARC) is formed in a plurality of holes and on a first surface of a layer of a semiconductor device. A scatterometry measurement on at least a portion of the BARC is performed to produce measurement diffraction data. A thickness of the BARC in the plurality of holes is predicted by comparing the first diffraction data to a model of diffraction data to provide a predicted thickness, tp, and it is determined if the predicted thickness, tp, is within a target thickness range, &Dgr;td. The forming of the BARC is controlled in response to the prediction of the BARC thickness. A corresponding thickness control device for controlling the BARC thickness is also disclosed.

摘要翻译： 描述形成半导体器件的方法。 底部抗反射涂层（BARC）形成在多个孔中以及在半导体器件的层的第一表面上。 执行至少一部分BARC的散射测量以产生测量衍射数据。 通过将第一衍射数据与衍射数据的模型进行比较以提供预测厚度tp来预测多个孔中的BARC的厚度，并且确定预测厚度tp是否在目标厚度范围内， DELTAtd。 响应于BARC厚度的预测，控制BARC的形成。 还公开了用于控制BARC厚度的相应的厚度控制装置。