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    METHODS OF PREPARING CONDUCTORS, CONDUCTORS PREPARED THEREFROM, AND ELECTRONIC DEVICES INCLUDING THE SAME
    33.
    发明申请
    METHODS OF PREPARING CONDUCTORS, CONDUCTORS PREPARED THEREFROM, AND ELECTRONIC DEVICES INCLUDING THE SAME 审中-公开
    制备导体的方法，制备的导体和包括其的电子器件

    公开(公告)号：US20170040089A1

    公开(公告)日：2017-02-09

    申请号：US15215825

    申请日：2016-07-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongmin LEE ,  Se Yun KIM ,  Jong Wook ROH ,  Doh Won JUNG ,  Sungwoo HWANG ,  Chan KWAK

    IPC: H01B13/00 ,  G06F3/041 ,  H01B5/02

    CPC classification number: H01L51/5203 ,  H01B1/08 ,  H01L51/442 ,  H05K3/00 ,  Y02E10/549

    Abstract: A method of preparing a conductor including a first conductive layer including a plurality of metal oxide nanosheets, the method including: preparing a coating liquid including a plurality of metal oxide nanosheets, wherein an intercalant is attached to a surface of the nanosheets, applying the coating liquid to a substrate to provide a first conductive layer including a plurality of metal oxide nanosheets, and performing a surface treatment on the first conductive layer to remove at least a portion of the intercalant.

    Abstract translation: 一种制备导体的方法，所述导体包括包括多个金属氧化物纳米片的第一导电层，所述方法包括：制备包括多个金属氧化物纳米片的涂布液，其中插入剂附着在所述纳米片的表面上，涂覆所述涂层 液体提供到衬底以提供包括多个金属氧化物纳米片的第一导电层，并且在第一导电层上进行表面处理以去除至少一部分插入剂。

    SEMICONDUCTOR DEVICES INCLUDING LINE IDENTIFIER
    38.
    发明公开
    SEMICONDUCTOR DEVICES INCLUDING LINE IDENTIFIER 审中-公开

    公开(公告)号：US20230215805A1

    公开(公告)日：2023-07-06

    申请号：US18114337

    申请日：2023-02-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yewon SHIN ,  Jaesun YUN ,  Seungjun LEE ,  Jongmin LEE

    IPC: H01L23/528 ,  H01L23/522 ,  H10B43/27 ,  H10B43/40

    CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of insulation layers and a plurality of electrode layers alternately stacked in a third direction intersecting with first and second directions. A plurality of channel structures extends through the stacked structure in the third direction. A first wiring group includes a plurality of first horizontal wirings disposed on the stacked structure that are arranged in the first direction and extends in the second direction. A second wiring group includes a plurality of second horizontal wirings disposed on the stacked structure that are arranged in the first direction and extends in the second direction. Each of the plurality of first and second horizontal wirings are connected to corresponding one of the plurality of channel structures. A first line identifier is disposed between the first wiring group and the second wiring group.

    DECOUPLING CAPACITOR STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    39.
    发明公开
    DECOUPLING CAPACITOR STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230189511A1

    公开(公告)日：2023-06-15

    申请号：US17945542

    申请日：2022-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin LEE

    IPC: H01L27/108

    CPC classification number: H01L27/10897

    Abstract: A decoupling capacitor structure includes an insulating division pattern, conductive pads, lower electrode sets, a support structure, a dielectric layer, and an upper electrode structure. The conductive pads are at opposite sides of the insulating division pattern. The lower electrode sets are spaced apart from each other in a horizontal direction on each conductive pad. The support structure contacts and connects sidewalls of the lower electrodes. The dielectric layer is on the lower electrodes and the support structure. The upper electrode structure is on the dielectric layer. The lower electrode sets include first lower electrodes adjacent to the insulating division pattern and second lower electrodes spaced apart from the first lower electrodes in the horizontal direction. The support structure defines an opening between the second lower electrodes. The opening is not formed between the first lower electrodes or between the first lower electrodes the second lower electrodes.

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