公开(公告)号：US09373723B2

公开(公告)日：2016-06-21

申请号：US14336153

申请日：2014-07-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tamae Takano ,  Atsuo Isobe

IPC: H01L27/14 ,  H01L29/786 ,  H01L27/12 ,  H01L27/13 ,  H01L29/06

CPC classification number: H01L29/78606 ,  H01L27/1214 ,  H01L27/1266 ,  H01L27/13 ,  H01L29/0603 ,  H01L29/78609 ,  H01L29/78636

Abstract: The present invention provides a semiconductor device which suppresses a short circuit and a leakage current between a semiconductor film and a gate electrode generated by a break or thin thickness of a gate insulating film in an end portion of a channel region of the semiconductor film, and the manufacturing method of the semiconductor device. Plural thin film transistors which each have semiconductor film provided over a substrate continuously, conductive films provided over the semiconductor film through a gate insulating film, source and drain regions provided in the semiconductor film which are not overlapped with the conductive films, and channel regions provided in the semiconductor film existing under the conductive films and between the source and drain regions. And impurity regions provided in the semiconductor film which is not overlapped with the conductive film and provided adjacent to the source and drain regions. Further, the conductive films are provided over the channel regions and regions of the semiconductor film which are provided adjacent to the channel regions.

公开(公告)号：US09293186B2

公开(公告)日：2016-03-22

申请号：US14208428

申请日：2014-03-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Naoaki Tsutsui ,  Atsuo Isobe ,  Wataru Uesugi ,  Takuro Ohmaru

IPC: G11C11/24 ,  G11C11/401 ,  G11C11/403

CPC classification number: G11C11/4093 ,  G11C11/24 ,  G11C11/401 ,  G11C11/403

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract translation: 存储器件包括：第一存储器电路，包括硅晶体管，包括硅晶体管的选择电路和包括氧化物半导体晶体管和存储电容器的第二存储器电路，其中存储电容器的一个端子连接到两个 氧化物半导体晶体管串联连接，第二存储电路的输出连接到选择电路的第二输入端，第二存储电路的输入端连接到选择电路的第一输入端或输出端 的第一存储器电路。

公开(公告)号：US09142679B2

公开(公告)日：2015-09-22

申请号：US13686281

申请日：2012-11-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Yoshinori Ieda ,  Masaharu Nagai

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/7869

Abstract: A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an oxide semiconductor layer is formed over the gate insulating layer; a first conductive layer and a second conductive layer are formed over the oxide semiconductor layer; a conductive film is formed over the first conductive layer and the second conductive layer; a resist mask is formed over the conductive film by performing electron beam exposure; and then a third conductive layer and a fourth conductive layer are formed over and in contact with the first conductive layer and the second conductive layer, respectively, by selectively etching the conductive film.

Abstract translation: 提供了包括具有短沟道长度的微小晶体管的半导体器件。 在栅电极层上形成栅极绝缘层; 在栅绝缘层上形成氧化物半导体层; 在所述氧化物半导体层上形成第一导电层和第二导电层; 在第一导电层和第二导电层上形成导电膜; 通过进行电子束曝光在导电膜上形成抗蚀剂掩模; 然后通过选择性地蚀刻导电膜，分别在第一导电层和第二导电层上形成第三导电层和第四导电层，并与第二导电层接触。

公开(公告)号：US09136361B2

公开(公告)日：2015-09-15

申请号：US14656125

申请日：2015-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sachiaki Tezuka ,  Atsuo Isobe ,  Takehisa Hatano ,  Kazuya Hanaoka

IPC: H01L29/66 ,  H01L21/465 ,  H01L21/463

CPC classification number: H01L29/66969 ,  H01L21/463 ,  H01L21/465 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/7869

Abstract: To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.

公开(公告)号：US08933455B2

公开(公告)日：2015-01-13

申请号：US14018463

申请日：2013-09-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroshi Shibata ,  Atsuo Isobe

IPC: H01L29/04 ,  H01L29/10 ,  H01L27/12 ,  G02F1/1362 ,  G02F1/1345 ,  H01L27/32 ,  H01L29/786

CPC classification number: H01L27/1255 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136277 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/3244 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78633

Abstract: To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.

Abstract translation: 为了提供一种通过在确保足够的存储电容器（Cs）的同时获得高开口率而具有高质量显示的液晶显示装置，并且同时通过分散电容器布线的负载（像素写入电流） 及时有效减轻负荷。 扫描线形成在与栅电极不同的层上，电容布线与信号线平行。 每个像素通过电介质连接到单独独立的电容器布线。 因此，可以避免由相邻像素的写入电流引起的电容器布线的电位变化，从而获得令人满意的显示图像。

公开(公告)号：US08841730B2

公开(公告)日：2014-09-23

申请号：US13895484

申请日：2013-05-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo Isobe

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/78603

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. A semiconductor device comprises a first single-crystal semiconductor layer including a first channel formation region and a first impurity region over a substrate having an insulating surface, a first gate insulating layer over the first single-crystal semiconductor layer, a gate electrode over the first gate insulating layer, a first interlayer insulating layer over the first gate insulating layer, a second gate insulating layer over the gate electrode and the first interlayer insulating layer, and a second single-crystal semiconductor layer including a second channel formation region and a second impurity region over the second gate insulating layer. The first channel formation region, the gate electrode, and the second channel formation region are overlapped with each other.

Abstract translation: 提供半导体器件和半导体器件的制造方法。 半导体器件包括：第一单晶半导体层，包括在具有绝缘表面的衬底上的第一沟道形成区域和第一杂质区域，在第一单晶半导体层上方的第一栅极绝缘层，第一单晶半导体层上的栅电极 栅极绝缘层，第一栅极绝缘层上的第一层间绝缘层，栅极电极和第一层间绝缘层之上的第二栅极绝缘层，以及包括第二沟道形成区域和第二杂质的第二单晶半导体层 区域。 第一沟道形成区域，栅极电极和第二沟道形成区域彼此重叠。

公开(公告)号：US08748241B2

公开(公告)日：2014-06-10

申请号：US13716899

申请日：2012-12-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo Isobe ,  Yutaka Okazaki ,  Kazuya Hanaoka ,  Shinya Sasagawa ,  Motomu Kurata

IPC: H01L21/339 ,  H01L21/00 ,  H01L21/84 ,  H01L21/76

CPC classification number: H01L27/1225 ,  H01L27/10879 ,  H01L27/1104 ,  H01L27/11521 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.

Abstract translation: 在栅极绝缘膜上形成与氧化物半导体膜重叠的第一导电膜，通过使用经受电子束曝光的抗蚀剂选择性蚀刻第一导电膜形成栅电极，在栅绝缘膜上形成第一绝缘膜 和栅电极，在栅电极未被露出的同时去除第一绝缘膜的一部分，在第一绝缘膜，抗反射膜，第一绝缘膜和栅极绝缘膜上形成防反射膜 使用经受电子束曝光的抗蚀剂选择性蚀刻，以及与氧化物半导体膜的一端接触的源极和与氧化物半导体膜的另一端接触的第一绝缘膜和漏电极的一端，以及 形成第一绝缘膜的另一端。

公开(公告)号：US20130207112A1

公开(公告)日：2013-08-15

申请号：US13755921

申请日：2013-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo Isobe ,  Yasuyuki Arai

IPC: H01L29/786

CPC classification number: H01L29/78693 ,  H01L27/1225 ,  H01L27/1255

Abstract: A semiconductor device having a novel structure is provided in which a transistor including an oxide semiconductor and a transistor including a semiconductor material which is not an oxide semiconductor are stacked. Further, a semiconductor device in which a semiconductor element and a capacitor are formed efficiently is provided. In a semiconductor device, a first semiconductor element layer including a transistor formed using a semiconductor material which is not an oxide semiconductor, such as silicon, and a second semiconductor element layer including a transistor formed using an oxide semiconductor are stacked. A capacitor is formed using a wiring layer, or a conductive film or an insulating film which is in the same layer as a conductive film or an insulating film of the second semiconductor element layer.

Abstract translation: 提供具有新颖结构的半导体器件，其中堆叠包括氧化物半导体的晶体管和包括不是氧化物半导体的半导体材料的晶体管。 此外，提供其中有效形成半导体元件和电容器的半导体器件。 在半导体器件中，堆叠包括使用不是诸如硅的氧化物半导体的半导体材料形成的晶体管的第一半导体元件层和包括使用氧化物半导体形成的晶体管的第二半导体元件层。 使用布线层或与第二半导体元件层的导电膜或绝缘膜处于同一层的导电膜或绝缘膜形成电容器。

公开(公告)号：US11868877B2

公开(公告)日：2024-01-09

申请号：US17588613

申请日：2022-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Takayuki Ikeda ,  Atsuo Isobe ,  Atsushi Miyaguchi ,  Shunpei Yamazaki

IPC: G06T1/20 ,  G06F1/3234 ,  G06N3/065 ,  G06F7/544

CPC classification number: G06N3/065 ,  G06F1/3243 ,  G06F7/5443 ,  G06T1/20

Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit. The first to third data retention circuits each include a transistor including an oxide semiconductor and a capacitor.

公开(公告)号：US11275993B2

公开(公告)日：2022-03-15

申请号：US16641821

申请日：2018-08-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Takayuki Ikeda ,  Atsuo Isobe ,  Atsushi Miyaguchi ,  Shunpei Yamazaki

IPC: G06T1/20 ,  G06F1/3234 ,  G06N3/063 ,  G06F7/544

Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit. The first to third data retention circuits each include a transistor including an oxide semiconductor and a capacitor.