公开(公告)号：US10153378B2

公开(公告)日：2018-12-11

申请号：US14851119

申请日：2015-09-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masahiro Takahashi ,  Tatsuya Honda ,  Takehisa Hatano

IPC: H01L29/12 ,  H01L29/786 ,  H01L29/24

Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.

公开(公告)号：US12062722B2

公开(公告)日：2024-08-13

申请号：US17164886

申请日：2021-02-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masahiro Takahashi ,  Tatsuya Honda ,  Takehisa Hatano

IPC: H01L29/786 ,  H01L29/00 ,  H01L29/04 ,  H01L29/12 ,  H01L29/20 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L29/772

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/78618 ,  H01L29/00 ,  H01L29/04 ,  H01L29/045 ,  H01L29/12 ,  H01L29/20 ,  H01L29/22 ,  H01L29/26 ,  H01L29/772

Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.

公开(公告)号：US09570594B2

公开(公告)日：2017-02-14

申请号：US15049761

申请日：2016-02-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takehisa Hatano ,  Sachiaki Tezuka ,  Atsuo Isobe

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/66 ,  H01L27/12 ,  H01L29/04 ,  H01L29/24 ,  H01L29/423 ,  H01L29/786 ,  H01L27/115 ,  H01L21/033 ,  H01L21/467

CPC classification number: H01L29/66969 ,  H01L21/0334 ,  H01L21/467 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/7869

Abstract: A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield. The semiconductor device has a structure including an oxide semiconductor film provided over a substrate having an insulating surface; a source electrode layer and a drain electrode layer which are provided in contact with side surfaces of the oxide semiconductor film and have a thickness larger than that of the oxide semiconductor film; a gate insulating film provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and a gate electrode layer provided in a depressed portion formed by a step between a top surface of the oxide semiconductor film and top surfaces of the source electrode layer and the drain electrode layer.

Abstract translation: 提供了一种小型化并且保持有利的特性的半导体器件。 此外，小型半导体器件具有高产率。 半导体器件具有包括设置在具有绝缘表面的衬底上的氧化物半导体膜的结构; 源极电极层和漏电极层，其设置成与氧化物半导体膜的侧表面接触并且具有比氧化物半导体膜的厚度大的厚度; 设置在所述氧化物半导体膜，所述源极电极层和所述漏极电极层上的栅极绝缘膜; 以及设置在由氧化物半导体膜的顶表面和源电极层和漏电极层的顶表面之间的台阶形成的凹陷部中的栅电极层。

公开(公告)号：US09117916B2

公开(公告)日：2015-08-25

申请号：US13646086

申请日：2012-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takehisa Hatano ,  Sachiaki Tezuka ,  Atsuo Isobe

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/66969 ,  H01L21/0334 ,  H01L21/467 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/7869

Abstract: A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield. The semiconductor device has a structure including an oxide semiconductor film provided over a substrate having an insulating surface; a source electrode layer and a drain electrode layer which are provided in contact with side surfaces of the oxide semiconductor film and have a thickness larger than that of the oxide semiconductor film; a gate insulating film provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and a gate electrode layer provided in a depressed portion formed by a step between a top surface of the oxide semiconductor film and top surfaces of the source electrode layer and the drain electrode layer.

Abstract translation: 提供了一种小型化并且保持有利的特性的半导体器件。 此外，小型半导体器件具有高产率。 半导体器件具有包括设置在具有绝缘表面的衬底上的氧化物半导体膜的结构; 源极电极层和漏电极层，其设置成与氧化物半导体膜的侧表面接触并且具有比氧化物半导体膜的厚度大的厚度; 设置在所述氧化物半导体膜，所述源极电极层和所述漏极电极层上的栅极绝缘膜; 以及设置在由氧化物半导体膜的顶表面和源电极层和漏电极层的顶表面之间的台阶形成的凹陷部中的栅电极层。

公开(公告)号：US09136361B2

公开(公告)日：2015-09-15

申请号：US14656125

申请日：2015-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sachiaki Tezuka ,  Atsuo Isobe ,  Takehisa Hatano ,  Kazuya Hanaoka

IPC: H01L29/66 ,  H01L21/465 ,  H01L21/463

CPC classification number: H01L29/66969 ,  H01L21/463 ,  H01L21/465 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/7869

Abstract: To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.

公开(公告)号：US10991829B2

公开(公告)日：2021-04-27

申请号：US16163917

申请日：2018-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masahiro Takahashi ,  Tatsuya Honda ,  Takehisa Hatano

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/00 ,  H01L29/04 ,  H01L29/12 ,  H01L29/20 ,  H01L29/22 ,  H01L29/26 ,  H01L29/772

Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.

公开(公告)号：US10008587B2

公开(公告)日：2018-06-26

申请号：US14459597

申请日：2014-08-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Toshihiko Saito ,  Takehisa Hatano ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Junichi Koezuka ,  Yuichi Sato ,  Shinji Ohno

IPC: H01L21/336 ,  H01L21/311 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L21/02 ,  H01L21/31

CPC classification number: H01L29/66969 ,  H01L21/02488 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.

公开(公告)号：US09269798B2

公开(公告)日：2016-02-23

申请号：US14736808

申请日：2015-06-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takehisa Hatano ,  Sachiaki Tezuka ,  Atsuo Isobe

IPC: H01L21/00 ,  H01L21/16 ,  H01L29/66 ,  H01L29/786 ,  H01L21/467 ,  H01L21/033

CPC classification number: H01L29/66969 ,  H01L21/0334 ,  H01L21/467 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/7869

Abstract: A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield. The semiconductor device has a structure including an oxide semiconductor film provided over a substrate having an insulating surface; a source electrode layer and a drain electrode layer which are provided in contact with side surfaces of the oxide semiconductor film and have a thickness larger than that of the oxide semiconductor film; a gate insulating film provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and a gate electrode layer provided in a depressed portion formed by a step between a top surface of the oxide semiconductor film and top surfaces of the source electrode layer and the drain electrode layer.

Abstract translation: 提供了一种小型化并且保持有利的特性的半导体器件。 此外，小型半导体器件具有高产率。 半导体器件具有包括设置在具有绝缘表面的衬底上的氧化物半导体膜的结构; 源极电极层和漏电极层，其设置成与氧化物半导体膜的侧表面接触并且具有比氧化物半导体膜的厚度大的厚度; 设置在所述氧化物半导体膜，所述源极电极层和所述漏极电极层上的栅极绝缘膜; 以及设置在由氧化物半导体膜的顶表面和源电极层和漏电极层的顶表面之间的台阶形成的凹陷部中的栅电极层。

公开(公告)号：US09018629B2

公开(公告)日：2015-04-28

申请号：US13646084

申请日：2012-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sachiaki Tezuka ,  Atsuo Isobe ,  Takehisa Hatano ,  Kazuya Hanaoka

IPC: H01L29/04 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L21/463 ,  H01L21/465 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/7869

Abstract: To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.

Abstract translation: 提供具有高电特性的小型化晶体管。 形成作为源电极层和漏电极层的导电膜以覆盖氧化物半导体层和沟道保护层，然后形成与氧化物半导体层和沟道保护层重叠的导电膜的区域， 通过化学机械抛光处理除去。 在除去作为源极电极层和漏极电极层的导电膜的一部分的工序中，不进行使用抗蚀剂掩模的蚀刻工序，所以可以精确地进行精加工。 通过沟道保护层，可以抑制由于在导电膜上的化学机械抛光处理对氧化物半导体层的损坏或膜厚度的降低。