公开(公告)号：US20140027762A1

公开(公告)日：2014-01-30

申请号：US13942866

申请日：2013-07-16

Applicant: Semiconductor Energy Laboratory Co. Ltd.

Inventor： Takuya TSURUME ,  Hideomi Suzawa

IPC: H01L29/24

CPC classification number: H01L29/24 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device is provided, which includes a first oxide semiconductor layer over a substrate, a second oxide semiconductor layer over and in contact the first oxide semiconductor layer, a source electrode and a drain electrode over the second oxide semiconductor layer, a gate insulating layer over the second oxide semiconductor layer, and a gate electrode over the gate insulating layer. The first oxide semiconductor layer has a step portion. The step portion is thinner than a portion other than the step portion. A surface of the step portion is in contact with the source electrode and the drain electrode.

Abstract translation: 提供一种半导体器件，其包括在衬底上的第一氧化物半导体层，在第一氧化物半导体层上方并与其接触的第二氧化物半导体层，在第二氧化物半导体层上的源电极和漏电极，栅极绝缘层 在第二氧化物半导体层上方，以及在栅极绝缘层上方的栅电极。 第一氧化物半导体层具有台阶部。 台阶部比台阶部以外的部分薄。 台阶部分的表面与源电极和漏电极接触。

公开(公告)号：US12148835B2

公开(公告)日：2024-11-19

申请号：US18211652

申请日：2023-06-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Tetsuhiro Tanaka ,  Hirokazu Watanabe ,  Yuhei Sato ,  Yasumasa Yamane ,  Daisuke Matsubayashi

IPC: H01L29/786 ,  H01L29/45 ,  H01L29/66

Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

公开(公告)号：US11646380B2

公开(公告)日：2023-05-09

申请号：US17564518

申请日：2021-12-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masayuki Sakakura ,  Hideomi Suzawa

IPC: H01L29/786 ,  H01L29/04 ,  H01L27/105 ,  H01L27/12 ,  H01L27/146 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L27/14616 ,  H01L29/04 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H10B99/00 ,  H01L29/7854

Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.

公开(公告)号：US11296231B2

公开(公告)日：2022-04-05

申请号：US16637384

申请日：2018-08-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuta Endo ,  Hideomi Suzawa

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/12 ,  H01L27/108

Abstract: A semiconductor device that can be highly integrated is provided.
The semiconductor device includes first and second transistors and first and second capacitors. Each of the first and second transistors includes a gate insulator and a gate electrode over an oxide. Each of the first and second capacitors includes a conductor, a dielectric over the conductor, and the oxide. The first and second transistors are provided between the first capacitor and the second capacitor. One of a source and a drain of the first transistor is also used as one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is also used as one electrode of the first capacitor. The other of the source and the drain of the second transistor is also used as one electrode of the second capacitor. The channel lengths of the first and second transistors are larger than the lengths in a direction parallel to short sides of fourth and fifth conductors.

公开(公告)号：US11296085B2

公开(公告)日：2022-04-05

申请号：US16645665

申请日：2018-09-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Hideomi Suzawa

IPC: H01L23/528 ,  H01L27/00 ,  H01L29/00 ,  H01L27/105 ,  H01L27/02 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first transistor, a second transistor, and an electrode. The first transistor and the second transistor include an oxide, a gate insulator over the oxide, and a gate. The electrode is connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor. The channel length of the first transistor is longer than the short side of the first conductor. The channel length of the second transistor is longer than the short side of the second conductor.

公开(公告)号：US11217704B2

公开(公告)日：2022-01-04

申请号：US16923160

申请日：2020-07-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masayuki Sakakura ,  Hideomi Suzawa

IPC: H01L29/786 ,  H01L29/04 ,  H01L27/105 ,  H01L27/12 ,  H01L27/146 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.

公开(公告)号：US10468506B2

公开(公告)日：2019-11-05

申请号：US16194444

申请日：2018-11-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata ,  Masashi Tsubuku

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L27/146

Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

公开(公告)号：US10374094B2

公开(公告)日：2019-08-06

申请号：US15597237

申请日：2017-05-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa

IPC: H01L29/12 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/7869 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78648

Abstract: A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

公开(公告)号：US10236389B2

公开(公告)日：2019-03-19

申请号：US15900845

申请日：2018-02-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Hideomi Suzawa ,  Sachiaki Tezuka ,  Tetsuhiro Tanaka ,  Toshiya Endo ,  Mitsuhiro Ichijo

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8258 ,  H01L29/423 ,  H01L29/49 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12

Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.

公开(公告)号：US20180240819A1

公开(公告)日：2018-08-23

申请号：US15916860

申请日：2018-03-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Koji Ono ,  Hideomi Suzawa

IPC: H01L27/12 ,  H01L29/49 ,  H01L29/45 ,  H01L29/423 ,  H01B5/14 ,  H01B13/00 ,  H01B1/02 ,  H01L21/768 ,  H01L21/3213 ,  C23F4/00

CPC classification number: H01L27/1214 ,  C23F4/00 ,  H01B1/02 ,  H01B5/14 ,  H01B13/0006 ,  H01B13/0036 ,  H01L21/32136 ,  H01L21/76838 ,  H01L27/12 ,  H01L27/124 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/495 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle α in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.