公开(公告)号：US09842939B2

公开(公告)日：2017-12-12

申请号：US15259294

申请日：2016-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Toshinari Sasaki ,  Kosei Noda ,  Mizuho Sato ,  Mitsuhiro Ichijo ,  Toshiya Endo

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606

Abstract: In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which faints a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×1020 atoms/cm3 is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.

公开(公告)号：US09768279B2

公开(公告)日：2017-09-19

申请号：US14263479

申请日：2014-04-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kosei Noda ,  Yuichi Sato ,  Yuta Endo

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L29/786 ,  H01L27/1156

CPC classification number: H01L29/66969 ,  H01L21/26586 ,  H01L27/1156 ,  H01L29/7869

Abstract: To provide a transistor formed using an oxide semiconductor film with reduced oxygen vacancies. To provide a semiconductor device that operates at high speed. To provide a highly reliable semiconductor device. To provide a miniaturized semiconductor device. The semiconductor device includes an oxide semiconductor film; a gate electrode overlapping with the oxide semiconductor film; a gate insulating film between the oxide semiconductor film and the gate electrode; and a protective insulating film that is above the oxide semiconductor film, the gate electrode, and the gate insulating film and includes a region containing phosphorus or boron.

公开(公告)号：US09553583B2

公开(公告)日：2017-01-24

申请号：US14570553

申请日：2014-12-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Masashi Tsubuku ,  Kosei Noda

IPC: H01L29/78 ,  H01L21/16 ,  H01L21/00 ,  G09G3/3233 ,  H03K19/003 ,  H03K19/096 ,  G09G3/20 ,  H01L27/12 ,  H01L29/786 ,  G09G3/32

CPC classification number: H01L27/1255 ,  G09G3/20 ,  G09G3/2092 ,  G09G3/3233 ,  G09G3/3291 ,  G09G3/36 ,  G09G3/3648 ,  G09G2300/0439 ,  G09G2300/08 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/184 ,  G11C19/28 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K17/161 ,  H03K19/00315 ,  H03K19/096

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed, a semiconductor device includes a first conductive layer over an insulating layer, a semiconductor layer over the first conductive layer, a second conductive layer over the semiconductor layer, a gate insulating layer over the second conductive layer, and a gate electrode over the gate insulating layer. The semiconductor device may further include wiring layers. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width, and may be 1×10−17 A or less per micrometer. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

Abstract translation: 为了降低晶体管的泄漏电流，可以抑制逻辑电路的故障，半导体器件包括绝缘层上的第一导电层，第一导电层上的半导体层，半导体层上的第二导电层， 在第二导电层上的栅极绝缘层，以及栅极绝缘层上的栅电极。 半导体器件还可以包括布线​​层。 逻辑电路包括晶体管，其包括具有沟道形成层的功能的氧化物半导体层，其中截止电流在沟道宽度中为每微米1×10-13A或更小，并且可以为1×10-17A 或更小。 作为时钟信号的第一信号，第二信号和第三信号被输入作为输入信号。 作为输出信号输出第四信号和第五信号，其电压状态根据输入的第一至第三信号而被设定。

公开(公告)号：US09537014B2

公开(公告)日：2017-01-03

申请号：US14723624

申请日：2015-05-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuki Tanemura ,  Tetsuhiro Tanaka ,  Kosei Noda

IPC: H01L29/12 ,  H01L29/786 ,  H01L27/12 ,  H01L29/51 ,  H01L29/792 ,  H01L27/088 ,  H01L27/11 ,  H01L27/115 ,  H01L21/66

CPC classification number: H01L29/7869 ,  H01L22/14 ,  H01L22/20 ,  H01L27/0883 ,  H01L27/1104 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/792

Abstract: Threshold voltage adjustment method of a semiconductor device is provided. In a semiconductor device in which at least one of transistors included in an inverter includes a semiconductor, a source electrode or a drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer provided between the gate electrode and the semiconductor, the potential of the gate electrode of the transistor that is higher than those of the source electrode and the drain electrode is held for a short time of 5 s or shorter, whereby electrons are trapped in the charge trap layer and the threshold voltage is increased. At this time, when the potential differences between the gate electrode and the source electrode, and the gate electrode and the drain electrode are different from each other, the threshold voltage of the transistor of the semiconductor device becomes appropriate.

Abstract translation: 提供半导体器件的阈值电压调整方法。 在其中包括在反相器中的至少一个晶体管包括半导体，与半导体电连接的源电极或漏电极，设置在栅电极和半导体之间的栅电极和电荷陷阱层的半导体器件中， 晶体管的栅电极的电位比源电极和漏电极的电位保持5秒以下的短时间，由此电子被捕获在电荷陷阱层中，并且阈值电压增加。 此时，当栅电极和源电极以及栅电极和漏电极之间的电位差彼此不同时，半导体器件的晶体管的阈值电压变得适当。

公开(公告)号：US09525034B2

公开(公告)日：2016-12-20

申请号：US13799246

申请日：2013-03-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Hiroyuki Miyake ,  Kei Takahashi ,  Kouhei Toyotaka ,  Masashi Tsubuku ,  Kosei Noda ,  Hideaki Kuwabara

IPC: H01L29/26 ,  H01L27/12 ,  H01L29/786

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

公开(公告)号：US09478564B2

公开(公告)日：2016-10-25

申请号：US14989927

申请日：2016-01-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masashi Tsubuku ,  Kosei Noda ,  Kouhei Toyotaka ,  Kazunori Watanabe ,  Hikaru Harada

IPC: H01L29/04 ,  H01L29/12 ,  H01L29/78 ,  H01L27/12 ,  H01L27/108 ,  H01L27/11 ,  H01L49/02 ,  H01L29/786 ,  G06F15/76 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7869 ,  G06F15/76 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1112 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78696

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

公开(公告)号：US09431546B2

公开(公告)日：2016-08-30

申请号：US14628439

申请日：2015-02-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Hiroyuki Miyake ,  Masashi Tsubuku ,  Kosei Noda

IPC: G05F3/16 ,  G05F1/00 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78696 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H02M3/073 ,  H02M3/158

Abstract: A transistor includes a gate, a source, and a drain, the gate is electrically connected to the source or the drain, a first signal is input to one of the source and the drain, and an oxide semiconductor layer whose carrier concentration is 5×1014/cm3 or less is used for a channel formation layer. A capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a second signal which is a clock signal is input to the second electrode. A voltage of the first signal is stepped up or down to obtain a third signal which is output as an output signal through the other of the source and the drain of the transistor.

Abstract translation: 晶体管包括栅极，源极和漏极，栅极电连接到源极或漏极，第一信号被输入到源极和漏极中的一个，以及载流子浓度为5× 1014 / cm3以下用于沟道形成层。 电容器包括第一电极和第二电极，第一电极电连接到晶体管的源极和漏极中的另一个，并且作为时钟信号的第二信号被输入到第二电极。 第一信号的电压被升高或降低以获得通过晶体管的源极和漏极中的另一个输出作为输出信号的第三信号。

公开(公告)号：US09419020B2

公开(公告)日：2016-08-16

申请号：US14339540

申请日：2014-07-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Atsushi Hirose ,  Masashi Tsubuku ,  Kosei Noda

IPC: H01L25/00 ,  H01L27/12 ,  H01L29/36 ,  H01L29/786 ,  H01L33/02 ,  H04R1/02 ,  H01L21/8234

CPC classification number: H01L27/1225 ,  H01L21/823412 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/156 ,  H01L27/3213 ,  H01L29/24 ,  H01L29/36 ,  H01L29/7869 ,  H01L29/78693 ,  H01L33/025 ,  H01L2924/0002 ,  H04M1/0266 ,  H04R1/02 ,  H01L2924/00

Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

公开(公告)号：US09396939B2

公开(公告)日：2016-07-19

申请号：US14678119

申请日：2015-04-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Toshinari Sasaki ,  Kosei Noda ,  Mizuho Sato

IPC: H01L21/322 ,  H01L21/02 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L21/02554 ,  H01L21/02488 ,  H01L21/02664 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.

公开(公告)号：US09236489B2

公开(公告)日：2016-01-12

申请号：US13845424

申请日：2013-03-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Masashi Tsubuku ,  Kosei Noda

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/66

Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.