公开(公告)号：US12278291B2

公开(公告)日：2025-04-15

申请号：US17296358

申请日：2019-11-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kentaro Sugaya ,  Ryota Hodo ,  Kenichiro Makino ,  Shuhei Nagatsuka

IPC: H01L29/786 ,  H01L21/308 ,  H01L27/12 ,  H01L29/66

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a plurality of transistors; each of the plurality of transistors includes a first insulator, a first oxide, a second oxide, a first conductor, a second conductor, a third oxide, a second insulator, and a third conductor; the third oxide included in one of the plurality of transistors and the third oxide included in another of the plurality of transistors, which is adjacent to the one of the plurality of transistors, are provided to be apart from each other in the channel width direction of the plurality of transistors; the second insulator included in one of the plurality of transistors includes a region continuous with the second insulator included in another of the plurality of transistors, which is adjacent to the one of the plurality of transistors; and the third conductor included in one of the plurality of transistors includes a region continuous with the third conductor included in another of the plurality of transistors, which is adjacent to the one of the plurality of transistors.

公开(公告)号：US11699465B2

公开(公告)日：2023-07-11

申请号：US17505110

申请日：2021-10-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Shuhei Nagatsuka

IPC: G11C5/06 ,  G11C11/4074 ,  H01L29/786 ,  G11C7/10 ,  H10B12/00 ,  G11C11/4091

CPC classification number: G11C5/063 ,  G11C7/1051 ,  G11C11/4074 ,  G11C11/4091 ,  H01L29/7869 ,  H10B12/30 ,  H10B12/50

Abstract: A memory device that operates at high speed is provided.
The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

公开(公告)号：US11205461B2

公开(公告)日：2021-12-21

申请号：US16625826

申请日：2018-06-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Shuhei Nagatsuka

IPC: G11C11/4091 ,  G11C7/10 ,  G11C5/06 ,  G11C11/4074 ,  H01L27/108 ,  H01L29/786

Abstract: A memory device that operates at high speed is provided.
The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

公开(公告)号：US10860080B2

公开(公告)日：2020-12-08

申请号：US16476642

申请日：2018-01-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Maeda ,  Shuhei Nagatsuka ,  Tatsuya Onuki ,  Kiyoshi Kato

IPC: G11C11/409 ,  G06F1/3234 ,  G11C5/14 ,  G11C14/00 ,  G11C16/30

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

公开(公告)号：US10658877B2

公开(公告)日：2020-05-19

申请号：US15822483

申请日：2017-11-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Akihiro Kimura

IPC: H02J7/00 ,  H02J50/40 ,  H02J50/10 ,  H02J50/27 ,  H01M10/44 ,  H04B1/3883 ,  H02J7/02

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

公开(公告)号：US10453846B2

公开(公告)日：2019-10-22

申请号：US14287285

申请日：2014-05-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

IPC: G11C11/24 ,  H01L27/105 ,  G11C8/08 ,  G11C11/403 ,  G11C11/405 ,  G11C11/408 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08

Abstract: A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.

公开(公告)号：US10236387B2

公开(公告)日：2019-03-19

申请号：US15262660

申请日：2016-09-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Shionoiri ,  Shuhei Nagatsuka ,  Hideki Uochi

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/544 ,  H01L21/66 ,  H01L23/495 ,  H01L23/31 ,  H01L27/32 ,  H05B33/08

Abstract: In a logic circuit including transistors with the same conductivity, a reduction in output voltage is prevented with use of at least three transistors and a capacitor. With use of an oxide semiconductor in a semiconductor layer of the transistor, a logic circuit with high output voltage and high withstand voltage is achieved. With use of the logic circuit, a semiconductor device with high output voltage and high withstand voltage is achieved.

公开(公告)号：US10217752B2

公开(公告)日：2019-02-26

申请号：US15591150

申请日：2017-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Tamae Moriwaka ,  Yuta Endo

IPC: H01L29/10 ,  H01L27/115 ,  H01L29/786 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  G11C11/24 ,  H01L29/24

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US10217736B2

公开(公告)日：2019-02-26

申请号：US14492412

申请日：2014-09-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Hidekazu Miyairi ,  Shuhei Nagatsuka

IPC: H01L27/06 ,  H01L27/12 ,  H01L27/108 ,  H01L27/1156

Abstract: A highly integrated semiconductor device including a transistor and a capacitor which occupies a small area for the required on-state current and required capacitance is provided. The semiconductor device includes a semiconductor, first and second conductive films each in contact with top and side surfaces of the semiconductor, a first insulating film in contact with the top and side surfaces of the semiconductor, a third conductive film facing the top and side surfaces of the semiconductor with the first insulating film therebetween, a second insulating film which is in contact with the first conductive film and comprises an opening, a fourth conductive film in contact with the opening, a third insulating film facing the opening with the fourth conductive film therebetween, and a fifth conductive film facing the fourth conductive film with the third insulating film therebetween.

公开(公告)号：US09954003B2

公开(公告)日：2018-04-24

申请号：US15430746

申请日：2017-02-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinpei Matsuda ,  Masayuki Sakakura ,  Yuki Hata ,  Shuhei Nagatsuka ,  Yuta Endo ,  Shunpei Yamazaki

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1222 ,  H01L27/1225 ,  H01L27/1237 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with high design flexibility is provided. A first transistor and a second transistor having electrical characteristics different from those of the first transistor are provided over the same layer without significantly increasing the number of manufacturing steps. For example, semiconductor materials with different electron affinities are used for a semiconductor layer in which a channel of the first transistor is formed and a semiconductor layer in which a channel of the second transistor is formed. This allows the threshold voltages of the first transistor and the second transistor to differ from each other. Forming a gate electrode using a damascene process enables miniaturization and high density of the transistors. Furthermore, a highly-integrated semiconductor device is provided.