公开(公告)号：US09131171B2

公开(公告)日：2015-09-08

申请号：US13772663

申请日：2013-02-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi Aoki ,  Takayuki Ikeda ,  Yurika Sato ,  Koji Dairiki

IPC: H04N5/335 ,  H04N5/374 ,  H04N5/378 ,  H04N5/232 ,  H04N7/18

CPC classification number: H04N5/335 ,  H04N5/23254 ,  H04N5/378 ,  H04N7/18

Abstract: Provided is an image sensor having a pixel includes a photoelectric conversion element; a capacitor which is connected between the photoelectric conversion element; a reset circuit which resets a potential of a node between the photoelectric conversion element and the capacitor; an amplifier circuit which outputs a signal corresponding to the potential of the node; and a switch which controls electrical conduction between the amplifier circuit and a vertical signal line. When the node is brought into an electrically floating state, the potential of the optical signal is stored in the node in a state of being inverted. When an optical signal is detected while the potential is stored in the node, the potential of the node increases in accordance with an output potential of the photoelectric conversion element, and thus the potential of the node corresponds to a difference in potential between the optical signals in different light-receiving periods.

Abstract translation: 提供一种具有像素的图像传感器，包括光电转换元件; 连接在光电转换元件之间的电容器; 复位电路，其复位所述光电转换元件与所述电容器之间的节点的电位; 输出对应于该节点的电位的信号的放大器电路; 以及控制放大器电路和垂直信号线之间的导通的开关。 当节点处于电浮动状态时，光信号的电位以倒置的状态存储在节点中。 当在电位存储在节点中时检测到光信号时，节点的电位根据光电转换元件的输出电位而增加，因此节点的电位对应于光信号之间的电位差 在不同的光接收期。

公开(公告)号：US20150116000A1

公开(公告)日：2015-04-30

申请号：US14587588

申请日：2014-12-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi Aoki ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/017581

Abstract: To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.

Abstract translation: 提供具有减小的电路面积和增加的操作速度的PLD。 在电路结构中，设置在可编程开关元件的输入端子和输出端子之间的晶体管的栅极在信号被输入到可编程开关元件的时段内处于电浮动状态。 该结构使得能够响应于从可编程逻辑元件提供的信号的升压效应来增加栅极的电压，从而抑制幅度电压的降低。 这可以通过诸如上拉电路的升压电路占据的区域来减小电路面积，并且增加操作速度。

公开(公告)号：US12002535B2

公开(公告)日：2024-06-04

申请号：US17640452

申请日：2020-09-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takeshi Aoki ,  Munehiro Kozuma ,  Masashi Fujita ,  Takahiko Ishizu

IPC: G11C11/24 ,  G11C7/06 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/54

CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/54

Abstract: A semiconductor device in which energy required for data transfer between an arithmetic device and a memory is reduced is provided. The semiconductor device includes a peripheral circuit and a memory cell array. The peripheral circuit has a function of a driver circuit and a control circuit for the memory cell array, and an arithmetic function. The peripheral circuit includes a sense amplifier circuit and an arithmetic circuit, and the memory cell array includes a memory cell and a bit line. The sense amplifier circuit has a function of determining whether the bit line is at a high level or a low level, and outputs the result to the arithmetic circuit. The arithmetic circuit has a function of performing a product-sum operation, the result of which is output from the semiconductor device.

公开(公告)号：US11777502B2

公开(公告)日：2023-10-03

申请号：US17441804

申请日：2020-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Munehiro Kozuma ,  Takeshi Aoki ,  Shuji Fukai ,  Fumika Akasawa ,  Sho Nagao

IPC: H03K19/08 ,  H03K17/56 ,  H01L27/12 ,  H01L27/13

CPC classification number: H03K19/08 ,  H03K17/56 ,  H01L27/1207 ,  H01L27/13

Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.

公开(公告)号：US11728354B2

公开(公告)日：2023-08-15

申请号：US17893247

申请日：2022-08-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi Aoki ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Hikaru Tamura

IPC: H01L27/146 ,  G09G3/36 ,  H01L29/786

CPC classification number: H01L27/14603 ,  G09G3/3648 ,  H01L27/14612 ,  H01L27/14616 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14641 ,  H01L27/14643 ,  H01L29/7869 ,  G09G2354/00

Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.

公开(公告)号：US11710751B2

公开(公告)日：2023-07-25

申请号：US17490009

申请日：2021-09-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Hikaru Tamura ,  Munehiro Kozuma ,  Masataka Ikeda ,  Takeshi Aoki

IPC: H01L27/146 ,  H01L29/786 ,  H01L31/105 ,  H04N25/63 ,  H04N25/75 ,  H04N25/76

CPC classification number: H01L27/14616 ,  H01L27/14603 ,  H01L27/14636 ,  H01L27/14643 ,  H01L29/7869 ,  H01L31/1055 ,  H04N25/63 ,  H04N25/75 ,  H04N25/76 ,  H01L27/14632

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

公开(公告)号：US11556771B2

公开(公告)日：2023-01-17

申请号：US16603710

申请日：2018-04-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shintaro Harada ,  Hiroki Inoue ,  Takeshi Aoki

IPC: G11C11/40 ,  G11C11/54 ,  G11C7/10 ,  G06N3/063

Abstract: Novel connection between neurons of a neural network is provided.
A perceptron included in the neural network includes a plurality of neurons; the neuron includes a synapse circuit and an activation function circuit; and the synapse circuit includes a plurality of memory cells. A bit line selected by address information for selecting a memory cell is shared by a plurality of perceptrons. The memory cell is supplied with a weight coefficient of an analog signal, and the synapse circuit is supplied with an input signal. The memory cell multiplies the input signal by the weight coefficient and converts the multiplied result into a first current. The synapse circuit generates a second current by adding a plurality of first currents and converts the second current into a first potential. The activation function circuit is a semiconductor device that converts the first potential into a second potential by a ramp function and supplies the second potential as an input signal of the synapse circuit included in the perceptron in a next stage.

公开(公告)号：US11314484B2

公开(公告)日：2022-04-26

申请号：US16609902

申请日：2018-05-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Kozuma ,  Takeshi Aoki ,  Seiichi Yoneda ,  Yoshiyuki Kurokawa

IPC: G06F7/544 ,  G06N3/063

Abstract: A semiconductor device having a novel structure is provided.
The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.

公开(公告)号：US10223194B2

公开(公告)日：2019-03-05

申请号：US15784669

申请日：2017-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi Aoki ,  Yoshiyuki Kurokawa

IPC: G11C11/00 ,  G06F11/10

Abstract: Data corrupted by a soft error is recovered. A storage device includes a first memory cell, a second memory cell, a sense circuit electrically connected to the first memory cell through a first sense line and to the second memory cell through a second sense line, a digital-analog converter circuit electrically connected to the first memory cell and the second memory cell through a bit line, and an analog-digital converter circuit. The digital-analog converter circuit has a function of applying voltages as first signals to the first memory cell and the second memory cell. Even when a soft error occurs in the first memory cell or the second memory cell, the storage device has a function of recovering data corrupted by the soft error because the sense circuit selects and outputs a higher one of the voltages applied to the first memory cell and the second memory cell.

公开(公告)号：US10109661B2

公开(公告)日：2018-10-23

申请号：US14990934

申请日：2016-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi Aoki ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Hikaru Tamura

IPC: G02F1/136 ,  H01L27/146 ,  G09G3/36 ,  H01L29/786

Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.