公开(公告)号：US20200350009A1

公开(公告)日：2020-11-05

申请号：US16669245

申请日：2019-10-30

Applicant: SK hynix Inc.

Inventor： Hyung Dong LEE ,  Tae Hoon KIM

IPC: G11C13/00

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a bit line, a word line crossing the bit line, and a memory cell coupled to and disposed between the bit line and the word line. In a read operation, when the word line, which is in a precharged state, is floated, the bit line is driven to increase a voltage level of the bit line, and stopped when the memory cell is turned on.

公开(公告)号：US20180033494A1

公开(公告)日：2018-02-01

申请号：US15726068

申请日：2017-10-05

Applicant: SK hynix Inc.

Inventor： Tae Hoon KIM

IPC: G11C29/50 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26 ,  G11C29/02 ,  G11C11/56 ,  G11C29/12

CPC classification number: G11C29/50004 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2029/5004

Abstract: A semiconductor memory device includes memory cells coupled to a word line; and a peripheral circuit configured to read first to kth page data from the memory cells by sequentially applying first to kth test voltages to the word line, where k is a natural number greater than 3, wherein the peripheral circuit is configured to gradually reduce times during which the first to kth test voltages are applied to the word line.

公开(公告)号：US20160329109A1

公开(公告)日：2016-11-10

申请号：US15211862

申请日：2016-07-15

Applicant: SK hynix Inc.

Inventor： Tae Hoon KIM

IPC: G11C29/38 ,  G11C16/14 ,  G11C29/44 ,  G11C16/26 ,  G11C29/12 ,  G11C29/36

CPC classification number: G11C29/50004 ,  G11C11/5642 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/12005 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G11C2029/5004

Abstract: A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes detecting a first group of changed bits between first and second page data, by comparing the first and second page data, which are read out using first and second test voltages from the memory cells, respectively, detecting a second group of changed bits between the second page data and a third page data, by comparing the second page data with the third page data read out from the memory cells using a third test voltage, comparing the numbers of the first and second groups of changed bits, and determining one of the first to third test voltages as a read voltage according to the comparing of the numbers of the first and second groups of changed bits.

Abstract translation: 提供一种半导体存储器件及其操作方法。 操作半导体存储器件的方法包括通过比较分别使用来自存储器单元的第一和第二测试电压读出的第一和第二页数据来检测第一和第二页数据之间的第一组改变位，检测 通过使用第三测试电压比较第二页面数据和从存储器单元读出的第三页面数据，比较第一和第二组数据的第二组数据， 根据第一组和第二组改变的比特的数量的比较，将第一至第三测试电压之一确定为读取电压。

公开(公告)号：US20160253124A1

公开(公告)日：2016-09-01

申请号：US14789441

申请日：2015-07-01

Applicant: SK hynix Inc.

Inventor： Tae Hoon KIM

IPC: G06F3/06

CPC classification number: G11C16/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5641

Abstract: A nonvolatile memory device includes a memory cell array including a data cell area, and a mode cell area that stores write mode information of the data cell area, a mode information storage block storing previous write mode information read out from the mode cell area in a previous read operation, and a control logic reading out the write mode information from the mode cell area comparing the read-out write mode information and the previous write mode information, and reading the data cell area in a read mode selected based on a comparison result.

Abstract translation: 非易失性存储器件包括存储单元阵列，包括数据单元区域和存储数据单元区域的写入模式信息的模式单元区域，存储从模块单元区域读出的先前写入模式信息的模式信息存储块， 先前的读取操作，以及控制逻辑，从模式单元区域读出写入模式信息，比较读出的写入模式信息和先前的写入模式信息，并且以基于比较结果选择的读取模式读取数据单元区域 。

公开(公告)号：US20150121168A1

公开(公告)日：2015-04-30

申请号：US14219775

申请日：2014-03-19

Applicant: SK hynix Inc.

Inventor： Tae Hoon KIM

IPC: G06F11/14 ,  G06F11/16

CPC classification number: G06F11/1435 ,  G06F11/1048 ,  G06F11/1666 ,  G11C8/06

Abstract: A memory system according to an embodiment of the present invention may include a semiconductor memory device including a plurality of memory areas, and a controller suitable for writing data to the semiconductor memory device and reading data from the semiconductor memory device. The controller provides a combined seed, which is used to copy data in a first memory area to a second memory area, to the semiconductor memory device, the combined seed being obtained by performing an operation on a de-randomizing seed corresponding to the first memory area and a randomizing seed corresponding to the second memory area.

Abstract translation: 根据本发明的实施例的存储器系统可以包括包括多个存储区域的半导体存储器件，以及适用于向半导体存储器件写入数据并从半导体存储器件读取数据的控制器。 所述控制器提供用于将第一存储器区域中的数据复制到第二存储器区域的组合种子到所述半导体存储器件，所述组合种子通过对对应于所述第一存储器的去随机化种子进行操作而获得 区域和对应于第二存储区域的随机化种子。

公开(公告)号：US20150113237A1

公开(公告)日：2015-04-23

申请号：US14221010

申请日：2014-03-20

Applicant: SK hynix Inc.

Inventor： Tae Hoon KIM

IPC: G06F3/06

CPC classification number: G11C16/3427 ,  G11C8/06 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/20 ,  G11C16/225 ,  G11C2211/5641

Abstract: A method of operating a data storing system includes performing a first copy operation of copying data stored in memory cells of first to nth word lines (n>1, and n is an integer) of a first memory block to first to nth pages of a word line of a second memory block; if a power is turned off, searching for a first erase page, which is recognized to be in an erase state, among the pages of the second memory block when the power comes back on; performing a first map-update on copied pages of the second memory block except for a set number of pages copied right before the first erase page; and performing a second copy operation from the first erase page.

Abstract translation: 操作数据存储系统的方法包括执行将第一存储块的第一至第n字线（n> 1和n为整数）的存储单元中存储的数据复制到第一至第n页的第一复制操作 第二存储块的字线; 如果电源被关闭，则当电源恢复打开时，在第二存储器块的页面中搜索识别为擦除状态的第一擦除页面; 对第二存储器块的复制页面执行第一映射更新，除了在第一擦除页面之前复制的设定页数; 以及从所述第一擦除页面执行第二复制操作。

公开(公告)号：US20140062557A1

公开(公告)日：2014-03-06

申请号：US13720992

申请日：2012-12-19

Applicant: SK HYNIX INC.

Inventor： Sung Woo HAN ,  Ic Su OH ,  Jun Ho LEE ,  Boo Ho JUNG ,  Sun Ki CHO ,  Yang Hee KIM ,  Tae Hoon KIM

IPC: H03K5/12

CPC classification number: H03K3/013 ,  G06F17/5022 ,  H03K5/12

Abstract: Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.

Abstract translation: 提供了一种减少包括多个输出缓冲器以输出数据的半导体装置的输出数据噪声的方法。 该方法包括以下步骤：将低数据驱动到多个输出缓冲器中的特定输出缓冲器，以及驱动数据从高电平转移到低电平到另一个输出缓冲器; 以及测量在特定输出缓冲器的输出数据中发生的数据噪声的大小，以及基于测量结果确定多个输出缓冲器的转换速率。