公开(公告)号：US20210249268A1

公开(公告)日：2021-08-12

申请号：US17244393

申请日：2021-04-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo ZANETTI ,  Simone RASCUNA' ,  Mario Giuseppe SAGGIO ,  Alfio GUARNERA ,  Leonardo FRAGAPANE ,  Cristina TRINGALI

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L29/872

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US20190214509A1

公开(公告)日：2019-07-11

申请号：US16357186

申请日：2019-03-18

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mario Giuseppe SAGGIO ,  Simone RASCUNA'

IPC: H01L29/872 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/16 ,  H01L23/535 ,  H01L21/768 ,  H01L21/225

CPC classification number: H01L29/872 ,  H01L21/2253 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/417 ,  H01L29/6606 ,  H01L29/66143

Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.

公开(公告)号：US20130095624A1

公开(公告)日：2013-04-18

申请号：US13706312

申请日：2012-12-05

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mario Giuseppe SAGGIO ,  Edoardo ZANETTI ,  Ferruccio FRISINA

IPC: H01L29/66

CPC classification number: H01L29/7811 ,  H01L21/0485 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7802

Abstract: An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the steps of: forming, on the semiconductor body, a first mask having a first window and a second window above a first surface portion and a second surface portion of the semiconductor body; forming, within the first and second surface portions of the semiconductor body underneath the first and second windows, at least one first conductive region and one second conductive region having a second conductivity type, the first conductive region and the second conductive region facing one another; forming a second mask on the semiconductor body, the second mask having a plurality of windows above surface portions of the first conductive region and the second conductive region; forming, within the first conductive region and the second conductive region and underneath the plurality of windows, a plurality of third conductive regions having the first conductivity type; removing completely the first and second masks; performing an activation thermal process of the first, second, and third conductive regions at a high temperature; and forming body and source regions.

Abstract translation: 一种用于制造具有第一导电类型的具有宽禁带隙的材料的半导体本体上的电子器件的方法的实施例。 该方法包括以下步骤：在半导体本体上形成第一掩模，该第一掩模在半导体本体的第一表面部分和第二表面部分之上具有第一窗口和第二窗口; 在第一和第二窗口下面的半导体本体的第一和第二表面部分内形成具有第二导电类型的至少一个第一导电区域和一个第二导电区域，第一导电区域和第二导电区域彼此面对; 在所述半导体主体上形成第二掩模，所述第二掩模在所述第一导电区域和所述第二导电区域的表面部分上方具有多个窗口; 在所述第一导电区域和所述第二导电区域内以及所述多个窗口下方形成具有所述第一导电类型的多个第三导电区域; 彻底清除第一和第二个面罩; 在高温下进行第一，第二和第三导电区域的激活热处理; 并形成体和源区。

公开(公告)号：US20250038060A1

公开(公告)日：2025-01-30

申请号：US18917464

申请日：2024-10-16

Applicant: STMicroelectronics S.r.l.

Inventor： Simone RASCUNA' ,  Claudio CHIBBARO ,  Alfio GUARNERA ,  Mario Giuseppe SAGGIO ,  Francesco LIZIO

IPC: H01L23/31 ,  H01L21/04 ,  H01L21/56 ,  H01L29/16

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

公开(公告)号：US20240079237A1

公开(公告)日：2024-03-07

申请号：US18363349

申请日：2023-08-01

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Mario Giuseppe SAGGIO ,  Cateno Marco CAMALLERI ,  Gabriele BELLOCCHI ,  Simone RASCUNA'

IPC: H01L21/04 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/0485 ,  H01L29/401 ,  H01L29/66068

Abstract: Method of manufacturing an electronic device, comprising forming an ohmic contact at an implanted region of a semiconductor body. Forming the ohmic contact provides for performing a high-temperature thermal process for allowing a reaction between a metal material and the material of the semiconductor body, for forming a silicide of the metal material. The step of forming the ohmic contact is performed prior to a step of forming one or more electrical structures which include materials that may be damaged by the high temperature of the thermal process of forming the silicide.

公开(公告)号：US20240014286A1

公开(公告)日：2024-01-11

申请号：US18345767

申请日：2023-06-30

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Mario Giuseppe SAGGIO ,  Cateno Marco CAMALLERI ,  Alfio GUARNERA

IPC: H01L29/49 ,  H01L29/16 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/4933 ,  H01L29/1608 ,  H01L29/7802 ,  H01L21/049 ,  H01L29/66068

Abstract: A power MOSFET device includes a semiconductor body having a first main surface. The semiconductor body includes an active area facing the first main surface. The power MOSFET device includes an isolated-gate structure, which extends over the active area and includes a gate-oxide layer, which is made of insulating material and extends over the first main surface, and a gate region buried in the gate-oxide layer so as to be electrically insulated from the semiconductor body. The gate region includes a gate layer of polysilicon and at least one first silicide electrical-modulation region and one second silicide electrical-modulation region, which extend in the gate layer so as to face a top surface of the gate layer and to be arranged alongside one another and spaced apart from one another in a first plane.

公开(公告)号：US20230134850A1

公开(公告)日：2023-05-04

申请号：US18045784

申请日：2022-10-11

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Salvatore CASCINO ,  Alfio GUARNERA ,  Mario Giuseppe SAGGIO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/04

Abstract: A semiconductor power device has a maximum nominal voltage and includes: a first conduction terminal and a second conduction terminal; a semiconductor body, containing silicon carbide and having a first conductivity type; body wells having a second conductivity type, housed in the semiconductor body and separated from one another by a body distance; source regions housed in the body wells; and floating pockets having the second conductivity type, formed in the semiconductor body at a distance from the body wells between a first face and a second face of the semiconductor body. The floating pockets are shaped and arranged relative to the body wells so that a maximum intensity of electrical field around the floating pockets is greater than a maximum intensity of electrical field around the body wells at least for values of a conduction voltage between the first conduction terminal and the second conduction terminal greater than a threshold voltage, the threshold voltage being less than the maximum nominal voltage.

公开(公告)号：US20230092543A1

公开(公告)日：2023-03-23

申请号：US18052510

申请日：2022-11-03

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone RASCUNA' ,  Claudio CHIBBARO ,  Alfio GUARNERA ,  Mario Giuseppe SAGGIO ,  Francesco LIZIO

IPC: H01L23/31 ,  H01L21/04 ,  H01L21/56 ,  H01L29/16

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

公开(公告)号：US20220246723A1

公开(公告)日：2022-08-04

申请号：US17579474

申请日：2022-01-19

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe SAGGIO ,  Alessia Maria FRAZZETTO ,  Edoardo ZANETTI ,  Alfio GUARNERA

IPC: H01L29/08 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66

Abstract: A vertical conduction MOSFET device includes a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body. The source region has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.

公开(公告)号：US20220208961A1

公开(公告)日：2022-06-30

申请号：US17559859

申请日：2021-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Patrick FIORENZA ,  Fabrizio ROCCAFORTE ,  Edoardo ZANETTI ,  Mario Giuseppe SAGGIO

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L21/76 ,  H01L21/761 ,  H01L29/66

Abstract: A MOSFET transistor device includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of the functional layer and each includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within the functional layer, and the body wells are separated from one another by surface-separation regions. Source regions having the first conductivity type are formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.