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公开(公告)号：US20230266387A1
公开(公告)日：2023-08-24
申请号：US18168496
申请日：2023-02-13
Applicant: STMicroelectronics International N.V.
Inventor： Rupesh SINGH , Ankur BAL
IPC: G01R31/317 , G01R31/28
CPC classification number: G01R31/31716 , G01R31/2851 , G01R31/31725
Abstract: An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serial izer without utilizing a deserializer.
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公开(公告)号：US20230168291A1
公开(公告)日：2023-06-01
申请号：US17969315
申请日：2022-10-19
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Sri Ram GUPTA
CPC classification number: G01R29/26 , H03K3/0315 , H03K3/037
Abstract: A measurement is made of jitter present in a jittery clock signal. A digital sinusoid generator circuit clocked by the jittery clock signal generates a pulse density modulation (PDM) signal corresponding to a sinusoid waveform. The PDM signal is converted by a sigma-delta modulator circuit to an oscillating frequency signal with an output of digital values digital values indicative of oscillating frequency signal phase. Responsive to the jittery clock signal, the digital values indicative of oscillating frequency signal phase are sampled. A digital differentiator circuit determines a digital difference between consecutive samples of the digital values indicative of oscillating frequency signal phase. The digital difference is processed by a digital signal processing circuit to generate a frequency spectrum and determine from signal-to-noise ratio a measurement of jitter in the jittery clock signal.
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公开(公告)号：US20230099514A1
公开(公告)日：2023-03-30
申请号：US17940236
申请日：2022-09-08
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Abhishek JAIN
Abstract: A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.
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公开(公告)号：US20230068753A1
公开(公告)日：2023-03-02
申请号：US17821398
申请日：2022-08-22
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Jeet Narayan TIWARI
Abstract: An integrated circuit includes a first circuit block operating with a first clock signal and a second circuit block operating with a second clock signal. The first circuit block includes a clock phase generator that receives the first clock signal and outputs a plurality of phase signals. The first circuit block includes a phase selector that receives the phase signals and the second clock signal and selects one of the phase signals based on the second clock signal. The first circuit block transmits data to the second circuit block based on the selected phase signal.
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公开(公告)号：US20220206987A1
公开(公告)日：2022-06-30
申请号：US17548101
申请日：2021-12-10
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.
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Patent Agency Ranking
公开(公告)号：US20210351780A1
公开(公告)日：2021-11-11
申请号：US17306178
申请日：2021-05-03
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Sharad GUPTA
Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.
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公开(公告)号：US20210211133A1
公开(公告)日：2021-07-08
申请号：US17131917
申请日：2020-12-23
Applicant: STMicroelectronics International N.V.
Inventor： Rupesh SINGH , Ankur BAL
Abstract: A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.
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公开(公告)号：US20210133124A1
公开(公告)日：2021-05-06
申请号：US17067967
申请日：2020-10-12
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
Abstract: Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.
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公开(公告)号：US20210110852A1
公开(公告)日：2021-04-15
申请号：US17015271
申请日：2020-09-09
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH , Vivek TRIPATHI
Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.
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公开(公告)号：US20140132434A1
公开(公告)日：2014-05-15
申请号：US13677674
申请日：2012-11-15
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Ankur BAL , Neha BHARGAVA , Anupam JAIN
Abstract: In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.
Abstract translation: 在一个实施例中，对一组输入样本进行滤波，以使用N抽头滤波器提供一组滤波样本。 N抽头滤波器的稳态响应输出样本由滤波样本集合的第N / 2个样本确定。
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