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    METHOD OF FABRICATING DISPLAY DEVICE
    31.
    发明申请
    METHOD OF FABRICATING DISPLAY DEVICE 有权
    制作显示装置的方法

    公开(公告)号：US20150037943A1

    公开(公告)日：2015-02-05

    申请号：US14081033

    申请日：2013-11-15

    Applicant: Samsung Display Co., Ltd.

    Inventor： Ji Young PARK ,  Dong Il KIM ,  Sang Gab KIM

    IPC: H01L27/12

    CPC classification number: H01L27/1288 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  H01L27/124

    Abstract: A method of fabricating a display device includes forming a thin-film transistor including a gate electrode, a source electrode and a drain electrode on a substrate, forming a first insulating layer and a second insulating layer on the thin-film transistor, forming a common electrode on the second insulating layer by depositing a common electrode material on the second insulating layer, plasma-treating a photoresist pattern on the common electrode material, and etching the common electrode material using the plasma-treated photoresist pattern as a mask, defining a contact hole in the second insulating layer which corresponds to the drain electrode using the plasma-treated photoresist pattern and the common electrode as a mask, forming a third insulating layer on the second insulating layer and the common electrode to expose the contact hole and the drain electrode and forming a pixel electrode connected to the drain electrode on the third insulating layer.

    Abstract translation: 制造显示装置的方法包括在衬底上形成包括栅电极，源电极和漏电极的薄膜晶体管，在薄膜晶体管上形成第一绝缘层和第二绝缘层，形成共同的 通过在第二绝缘层上沉积公共电极材料，等离子体处理公共电极材料上的光致抗蚀剂图案，以及使用等离子体处理的光致抗蚀剂图案作为掩模蚀刻公共电极材料，限定接触 使用等离子体处理的光致抗蚀剂图案和公共电极作为掩模对应于漏电极的第二绝缘层中的孔，在第二绝缘层和公共电极上形成第三绝缘层，以暴露接触孔和漏电极 以及在所述第三绝缘层上形成连接到所述漏电极的像素电极。

    THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME
    32.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20140183535A1

    公开(公告)日：2014-07-03

    申请号：US13875722

    申请日：2013-05-02

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Shin Il CHOI ,  Sang Gab KIM ,  Su Bin BAE ,  Yu-Gwang JEONG

    IPC: H01L27/12

    CPC classification number: H01L27/124 ,  H01L27/1248 ,  H01L27/322 ,  H01L27/3248

    Abstract: A thin film transistor array panel according to an exemplary embodiment of the invention includes: a substrate, a gate line disposed on the substrate and including a gate electrode, a gate insulating layer disposed on the gate line, a semiconductor disposed on the gate insulating layer, a data line disposed on the semiconductor and including a source electrode, a drain electrode disposed on the semiconductor and opposite to the source electrode, a color filter disposed on the gate insulating layer, the data line and the drain electrode, an overcoat disposed on the color filter and including an inorganic material, a contact hole defined in the color filter and the overcoat, where the contact hole exposes the drain electrode, and a pixel electrode disposed on the overcoat and connected through the contact hole to the drain electrode, in which a plane shape of the contact hole in the overcoat and a plane shape of the contact hole in the color filter are substantially the same as each other.

    Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：衬底，设置在衬底上并包括栅电极的栅极线，设置在栅极线上的栅极绝缘层，设置在栅极绝缘层上的半导体 ，设置在半导体上的数据线，包括源电极，设置在半导体上并与源电极相对的漏电极，布置在栅绝缘层上的滤色器，数据线和漏电极， 所述滤色器包括无机材料，所述滤色器中限定的接触孔和所述外涂层，其中所述接触孔暴露于所述漏电极，以及设置在所述外涂层上并通过所述接触孔连接到所述漏电极的像素电极， 外涂层中的接触孔的平面形状和滤色器中的接触孔的平面形状基本上与每个 r。

    DISPLAY PANEL AND METHOD FOR FABRICATING THE SAME
    35.
    发明公开
    DISPLAY PANEL AND METHOD FOR FABRICATING THE SAME 审中-公开

    公开(公告)号：US20230180526A1

    公开(公告)日：2023-06-08

    申请号：US17880744

    申请日：2022-08-04

    Applicant: Samsung Display Co., LTD.

    Inventor： Dae Won CHOI ,  Sang Gab KIM ,  Su Bin BAE ,  Yun Jong YEO ,  Da Woon JUNG ,  Yu Gwang JEONG

    IPC: H01L27/32 ,  H01L51/50 ,  H01L51/56

    CPC classification number: H01L27/3246 ,  H01L51/5056 ,  H01L51/5072 ,  H01L51/56 ,  H01L2251/308 ,  H01L2227/323

    Abstract: A display panel includes: a plurality of first electrodes disposed on a via-layer and corresponding to a plurality of pixel areas, respectively; a pixel-defining layer disposed on the via-layer; first opening parts corresponding to central portions of the first electrodes and penetrating through the pixel-defining layer; electrode undercuts corresponding to edges of the first opening parts and provided as gaps between the first electrodes and the pixel-defining layer; a plurality of second opening parts corresponding to peripheries of the first electrodes, respectively, and penetrating through the pixel-defining layer; and via-grooves corresponding to the second opening parts and defined on an upper surface of the via-layer; via-undercuts provided by the pixel-defining layer around the second opening parts and the via-layer around the via-grooves.

    LIGHT EMITTING DIODE DEVICE AND METHOD OF MANUFACTURING THE SAME
    38.
    发明申请
    LIGHT EMITTING DIODE DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200091393A1

    公开(公告)日：2020-03-19

    申请号：US16691495

    申请日：2019-11-21

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Su Bin BAE ,  Yu Gwang JEONG ,  Shin Il CHOI ,  Joon Geol LEE ,  Sang Gab KIM

    IPC: H01L33/62 ,  H01L33/00 ,  H01L21/306

    Abstract: A light emitting diode device includes a thin film transistor substrate having a plurality of light emitting areas, a first diode electrode and a second diode electrode on the thin film transistor substrate, a first passivation pattern between the first diode electrode and the second diode electrode, a plurality of micro light emitting diodes on the first passivation pattern, a first bridge pattern on the micro light emitting diodes and electrically connecting the first diode electrode to the micro light emitting diodes, and a second bridge pattern on the first bridge pattern and electrically connecting the second diode electrode to the micro light emitting diodes, wherein each sidewall of each of the micro light emitting diodes and each sidewall of the first passivation pattern form a same plane.

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