公开(公告)号：US11380700B2

公开(公告)日：2022-07-05

申请号：US16842907

申请日：2020-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Taemok Gwon ,  Youngbum Woo

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/07

Abstract: A vertical memory device includes lower circuit patterns, a second substrate, a capacitor, gate electrodes, and a channel. The lower circuit patterns are formed on a first substrate including first, second and third regions. Contact plugs are formed in the second region. Through vias are formed in the third region. The second substrate is formed on the lower circuit patterns. The capacitor is formed on the lower circuit patterns, and includes a first conductor, a dielectric layer structure, and a second conductor. The first conductor is spaced apart from the second substrate at the same height as the second substrate. The dielectric layer structure is formed on the first conductor. The second conductor is formed on the dielectric layer structure. The gate electrodes are spaced apart from each other on the second substrate in a vertical direction. The channel extends through the gate electrodes in the vertical direction.

公开(公告)号：US11217603B2

公开(公告)日：2022-01-04

申请号：US16850097

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Seonho Yoon ,  Bonghyun Choi

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556

Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

公开(公告)号：US20210327894A1

公开(公告)日：2021-10-21

申请号：US17359771

申请日：2021-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Kwang-soo Kim ,  GEUNWON LIM ,  JISUNG CHEON

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.

公开(公告)号：US20210287986A1

公开(公告)日：2021-09-16

申请号：US17060851

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemok Gwon ,  Junhyoung Kim ,  Chadong Yeo ,  Youngbum Woo

IPC: H01L23/522 ,  H01L29/10 ,  H01L23/532

Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.

公开(公告)号：US10910396B2

公开(公告)日：2021-02-02

申请号：US16444716

申请日：2019-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Geunwon Lim ,  Kwang-soo Kim

IPC: H01L27/11575 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes a plurality of first insulating layers vertically stacked on a peripheral logic structure, second insulating layers stacked alternately with the first insulating layers, conductive layers stacked alternately with the first insulating layers and disposed on sidewalls of the second insulating layers, through-interconnections penetrating the first insulating layers and the second insulating layers so as to be connected to the peripheral logic structure, and a first conductive line electrically connected to a plurality of first conductive layers of the conductive layers.

公开(公告)号：US20250120080A1

公开(公告)日：2025-04-10

申请号：US18666888

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Bumkyu Kang ,  Sehoon Lee ,  Sukkang Sung

IPC: H10B43/27 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a first substrate structure, and a second substrate structure connected to the first substrate structure and including circuit elements and second bonding metal layers. The first substrate structure includes gate electrodes stacked along a first direction, a supporter layer on the gate electrodes, channel structures extending along the first direction while penetrating the gate electrodes, separation regions extending in the first direction and a second direction by penetrating through the gate electrodes, and first bonding metal layers connected to the second bonding metal layers. The separation regions respectively include first regions spaced apart from each other along the second direction and a second region surrounding side surfaces of the first regions and extending in the second direction. The first regions and the channel structures penetrate the supporter layer, and a portion of a lower surface of the supporter layer is in contact with the second region.

公开(公告)号：US12165976B2

公开(公告)日：2024-12-10

申请号：US17861700

申请日：2022-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Joongshik Shin ,  Kwangsoo Kim

IPC: H10B41/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A three-dimensional semiconductor device may include a substrate having a cell area and an extension area, a word line stack disposed above the substrate, the word line stack including mold layers and word lines alternately stacked, vertical channel structures vertically penetrating the word line stack in the cell area, and a first extension through-via structure vertically penetrating the word line stack in the extension area. The first extension through-via structure may include a first via plug and a first via liner layer surrounding sidewalls of the first via plug. The first via liner layer may include first dents respectively disposed at the same levels horizontally as the word lines of the word line stack.

公开(公告)号：US12133384B2

公开(公告)日：2024-10-29

申请号：US18352182

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon ,  Yoonhwan Son ,  Seungmin Lee

IPC: H10B43/20 ,  H10B43/30 ,  H10B43/40

CPC classification number: H10B43/20 ,  H10B43/30 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US12133381B2

公开(公告)日：2024-10-29

申请号：US17497200

申请日：2021-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Taemok Gwon ,  Junhyoung Kim ,  Hyunjae Kim ,  Youngbum Woo ,  Jongin Yun

IPC: H10B41/27 ,  G11C5/06 ,  H01L23/538 ,  H01L29/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H10B43/27

Abstract: A semiconductor device includes a first substrate including an impurity region including impurities of a first conductivity type, circuit devices on the first substrate, a lower interconnection structure electrically connected to the circuit devices, a second substrate on the lower interconnection structure and including semiconductor of the first conductivity type, gate electrodes on the second substrate and stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, channel structures penetrating the gate electrodes, and a connection structure. The channel structures may extend perpendicular to the second substrate. The channel structures may include a channel layer. The connection structure may connect the impurity region of the first substrate to the second substrate, and the connection structure may include a via including a semiconductor of a second conductivity type.

公开(公告)号：US20240312938A1

公开(公告)日：2024-09-19

申请号：US18674610

申请日：2024-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Taemok Gwon ,  Seungmin Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L24/08 ,  H01L23/5226 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes first gate electrodes, a first channel structure penetrating the first gate electrodes and including a first channel layer and a first channel filling insulating layer, second gate electrodes above the first gate electrodes, a second channel structure penetrating the second gate electrodes and including a second channel layer and a second channel filling insulating layer, and a central wiring layer between the first gate electrodes and the second gate electrodes and connected to the first channel layer and the second channel layer, wherein the first channel layer and the second channel layer are connected to each other in a region surrounded by the central wiring layer, and the first channel filling insulating layer and the second channel filling insulating layer are connected to each other in a region surrounded by the central wiring layer.