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    Memory controller and memory system including the same
    31.
    发明授权
    Memory controller and memory system including the same 有权

    公开(公告)号：US11269723B2

    公开(公告)日：2022-03-08

    申请号：US16988931

    申请日：2020-08-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sanguhn Cha ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho

    IPC: G06F11/10 ,  H03M13/11 ,  G06F11/07 ,  H03M13/15

    Abstract: A memory controller controls a memory module including data chips and first and second parity chips. The memory controller includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder receives error information signals associated with the data chips, performs an ECC decoding on a codeword set from the memory module using the parity check matrix to generate a first syndrome and a second syndrome, and corrects bit errors in a user data set based on the error information signals and the second syndrome. The bit errors are generated by a row fault and uncorrectable using the first syndrome and the second syndrome. Each of the error information signals includes row fault information indicating whether the row fault occurs in at least one of memory cell rows in corresponding one of the data chips.

    Semiconductor memory devices and memory systems
    32.
    发明授权
    Semiconductor memory devices and memory systems 有权

    公开(公告)号：US11170868B2

    公开(公告)日：2021-11-09

    申请号：US16864787

    申请日：2020-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yesin Ryu ,  Sanguhn Cha ,  Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee ,  Youngcheon Kwon ,  Jaeyoun Youn

    IPC: G11C29/00 ,  G11C29/42 ,  G11C29/14 ,  G11C7/10 ,  G11C29/44 ,  G11C29/12

    Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.

    MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME
    33.
    发明申请
    MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20210208967A1

    公开(公告)日：2021-07-08

    申请号：US16988931

    申请日：2020-08-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SANGUHN CHA ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho

    IPC: G06F11/10 ,  G06F11/07 ,  H03M13/15 ,  H03M13/11

    Abstract: A memory controller controls a memory module including data chips and first and second parity chips. The memory controller includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder receives error information signals associated with the data chips, performs an ECC decoding on a codeword set from the memory module using the parity check matrix to generate a first syndrome and a second syndrome, and corrects bit errors in a user data set based on the error information signals and the second syndrome. The bit errors are generated by a row fault and uncorrectable using the first syndrome and the second syndrome. Each of the error information signals includes row fault information indicating whether the row fault occurs in at least one of memory cell rows in corresponding one of the data chips.

    Error correction circuit, memory system, and error correction method
    34.
    发明授权
    Error correction circuit, memory system, and error correction method 有权

    公开(公告)号：US12212339B2

    公开(公告)日：2025-01-28

    申请号：US17984430

    申请日：2022-11-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myungkyu Lee ,  Kijun Lee ,  Sunghye Cho ,  Sungrae Kim

    IPC: H03M13/15 ,  H03M13/00

    Abstract: An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.

    MEMORY CONTROLLERS AND MEMORY SYSTEMS
    35.
    发明公开
    MEMORY CONTROLLERS AND MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20240281323A1

    公开(公告)日：2024-08-22

    申请号：US18469894

    申请日：2023-09-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Jiho Kim ,  Kijun Lee ,  Kyomin Sohn

    IPC: G06F11/10

    CPC classification number: G06F11/1044

    Abstract: A memory controller including a processor and configured to control a memory module including a plurality of data chips and at least one parity chip includes an error correction code (ECC) engine, the ECC engine including an ECC decoder to correct Q symbols errors in a codeword set read from the memory module, Q is a maximum natural number equal to or less than P and P is a natural number equal to or greater than four. The ECC decoder is configured to generate a syndrome including first through P-th syndrome symbols based on the read codeword set by using a parity check matrix and to perform a first ECC decoding to correct a single symbol error in the read codeword set based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second through P-th syndrome symbols.

    Memory controllers, memory systems, and memory modules
    39.
    发明授权
    Memory controllers, memory systems, and memory modules 有权

    公开(公告)号：US11815997B2

    公开(公告)日：2023-11-14

    申请号：US17814964

    申请日：2022-07-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Suhun Lim ,  Kijun Lee ,  Myungkyu Lee ,  Eunchul Kwon ,  Hoyoun Kim ,  Jongmin Lee

    IPC: H03M13/00 ,  G06F11/10 ,  G06F11/07 ,  G06F17/16 ,  H03M13/15

    CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F17/16 ,  H03M13/1575

    Abstract: A memory controller includes an error correction code (ECC) engine and an error managing circuit. The ECC engine is configured to, during a read operation, perform an ECC decoding on a read codeword set to generate a first and second syndrome associated with a correctable error in a user data set included in the read codeword set, correct the correctable error based on the first syndrome and the second syndrome, and provide the second syndrome to the error managing circuit. The error managing circuit is configured to accumulate second syndromes associated with a plurality of correctable errors and obtained through a plurality of read operations as a plurality of second syndromes, store the plurality of second syndromes, compare the plurality of second syndromes with an error pattern set, and predict an occurrence of an uncorrectable error associated with the correctable error in a memory region based on the comparison.

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