公开(公告)号：US20250036299A1

公开(公告)日：2025-01-30

申请号：US18795406

申请日：2024-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-HOON CHOI ,  SANG-WAN NAM ,  SANGYONG YOON ,  KOOKHYUN CHO

IPC: G06F3/06

Abstract: A memory package includes a printed circuit board, a first memory device that is stacked on the printed circuit board, and a second memory device stacked on the first memory device. The first memory device includes a first one-time programmable (OTP) block, the second memory device includes a second OTP block different from the first OTP block, and a horizontal distance from one side of the first memory device to the first OTP block is different from a horizontal distance from one side of the second memory device to the second OTP block.

公开(公告)号：US20230178154A1

公开(公告)日：2023-06-08

申请号：US18103754

申请日：2023-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WON-TAECK JUNG ,  SANG-WAN NAM ,  JINWOO PARK ,  JAEYONG JEONG

IPC: G11C16/20 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/20 ,  G11C16/08 ,  G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  H10B41/27

Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.

公开(公告)号：US20230056261A1

公开(公告)日：2023-02-23

申请号：US17982255

申请日：2022-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： BONGSOON LIM ,  SANG-WAN NAM ,  SANG-WON PARK ,  SANG-WON SHIM ,  HONGSOO JEON ,  YONGHYUK CHOI

IPC: H01L23/535 ,  H01L27/11573 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.

公开(公告)号：US20200066347A1

公开(公告)日：2020-02-27

申请号：US16669920

申请日：2019-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANG-WAN NAM ,  WON-TAECK JUNG

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/24 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10

Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.

公开(公告)号：US20180292989A1

公开(公告)日：2018-10-11

申请号：US15869769

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-HOON LEE ,  EUN-SUK CHO ,  WOO-PYO JEONG ,  SANG-WAN NAM ,  JUNG-HO SONG ,  YUN-HO HONG ,  JAE-HOON LEE

IPC: G06F3/06 ,  H01L27/11573 ,  H01L27/11582 ,  H01L21/265 ,  H01L27/02

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G11C7/106 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/32 ,  H01L21/265 ,  H01L27/0207 ,  H01L27/11573 ,  H01L27/11582

Abstract: A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.

公开(公告)号：US20180053554A1

公开(公告)日：2018-02-22

申请号：US15681479

申请日：2017-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANG-WAN NAM ,  DAESEOK BYEON ,  CHIWEON YOON

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/28

CPC classification number: G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/107 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3459 ,  G11C2216/16

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder circuit. The row decoder circuit turns on memory cells of a plurality of cell strings of a selected memory block after applying a first prepulse to a first dummy word line connected to first dummy memory cells after applying a second prepulse to a second dummy word line connected to second dummy memory cells.

公开(公告)号：US20170194058A1

公开(公告)日：2017-07-06

申请号：US15461835

申请日：2017-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHI WEON YOON ,  DONGHYUK CHAE ,  JAE-WOO PARK ,  SANG-WAN NAM

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/16 ,  H01L29/792

Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

公开(公告)号：US20160035431A1

公开(公告)日：2016-02-04

申请号：US14880820

申请日：2015-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANG-WAN NAM ,  WON-TAECK JUNG

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/24

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3427

Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.