公开(公告)号：US09727412B2

公开(公告)日：2017-08-08

申请号：US14729656

申请日：2015-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Chul-Woo Park ,  Seong-Jin Jang ,  Hoi-Ju Chung ,  Sang-Uhn Cha

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G11C29/04

CPC classification number: G06F11/1008 ,  G06F11/1004 ,  G06F11/1024 ,  G06F11/1068 ,  G06F11/1666 ,  G11C2029/0411

Abstract: A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

公开(公告)号：US11239960B2

公开(公告)日：2022-02-01

申请号：US17079627

申请日：2020-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi-ju Chung ,  Sang-Uhn Cha ,  Hyun-Joong Kim

IPC: H04L1/24 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.

公开(公告)号：US11231996B2

公开(公告)日：2022-01-25

申请号：US17137535

申请日：2020-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Ho-Young Song ,  Hyun-Joong Kim

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/00 ,  G11C29/04

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

公开(公告)号：US11031065B2

公开(公告)日：2021-06-08

申请号：US17024259

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn Cha ,  Hyun-Gi Kim ,  Hoon Sin ,  Ye-Sin Ryu ,  In-Woo Jun

IPC: G11C7/00 ,  G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US10884852B2

公开(公告)日：2021-01-05

申请号：US16228560

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Seo ,  Kwang-Il Park ,  Seung-Jun Bae ,  Sang-Uhn Cha

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G11C11/4093 ,  H01L25/065

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

公开(公告)号：US10671478B2

公开(公告)日：2020-06-02

申请号：US15693673

申请日：2017-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uhn Cha ,  Ye-Sin Ryu

IPC: G06F11/10 ,  G11C29/42 ,  G06F11/07 ,  G11C29/44 ,  G06F3/06 ,  G11C29/52 ,  G11C13/00 ,  G06F12/02

Abstract: A scrubbing controller of a semiconductor memory device includes a scrubbing address generator and a weak codeword address generator. The scrubbing address generator generates a scrubbing address for all codewords in a first bank array of a plurality of bank arrays in a first scrubbing mode. The scrubbing address is associated with a normal scrubbing operation and changes in response to an internal scrubbing signal and a scrubbing command. The weak codeword address generator generates a weak codeword address for weak codewords in the first bank array in a second scrubbing mode. The weak codeword address is associated with a weak scrubbing operation and is generated in response to the internal scrubbing signal.

公开(公告)号：US10476529B2

公开(公告)日：2019-11-12

申请号：US15789653

申请日：2017-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uhn Cha ,  Ye-Sin Ryu ,  Young-Sik Kim ,  Su-Yeon Doo

IPC: G06F11/10 ,  H03M13/29 ,  H03M13/09

Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.

公开(公告)号：US10404286B2

公开(公告)日：2019-09-03

申请号：US15664295

申请日：2017-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon Sin ,  Sang-Uhn Cha ,  Ye-Sin Ryu ,  Seong-Jin Cho

IPC: G06F11/10 ,  H03M13/29 ,  H03M13/09 ,  H03M13/13

Abstract: A memory module includes data memories and at least one parity memory. Each of the data memories includes a first memory cell array with a first memory region to store data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits to perform error detection/correction associated with the data set. The at least one parity memory includes a second memory cell array with a first parity region to store parity bits associated with user data set corresponding to all of the data set stored in each of the data memories and a second parity region to store second parity bits for error detection/correction associated with the parity bits.

公开(公告)号：US10355833B2

公开(公告)日：2019-07-16

申请号：US16032544

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Hyun-Joong Kim

IPC: H04L1/24 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.

公开(公告)号：US20180323915A1

公开(公告)日：2018-11-08

申请号：US16032544

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Hyun-Joong Kim

IPC: H04L1/24 ,  G11C29/52

CPC classification number: H04L1/24 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.