公开(公告)号：US20250089320A1

公开(公告)日：2025-03-13

申请号：US18955290

申请日：2024-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonchoo CHO ,  Kyung-Eun BYUN ,  Keunwook SHIN ,  Hyeonjin SHIN

IPC: H01L29/04 ,  H01L23/522 ,  H01L29/16 ,  H01L29/161 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes a metal layer, a semiconductor layer in electrical contact with the metal layer, a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure, and a metal compound layer disposed between the 2D material layer and the semiconductor layer.

公开(公告)号：US20230077783A1

公开(公告)日：2023-03-16

申请号：US18056446

申请日：2022-11-17

Applicant: Samsung Electronics Co.,Ltd

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L29/24 ,  H01L29/423

Abstract: A field effect transistor includes a substrate, a source electrode and a drain electrode on the substrate and apart from each other in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has ends contacting the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.

公开(公告)号：US20230076900A1

公开(公告)日：2023-03-09

申请号：US18055565

申请日：2022-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

公开(公告)号：US20220320425A1

公开(公告)日：2022-10-06

申请号：US17836435

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Minhyun LEE ,  Dovran AMANOV ,  Renjing XU ,  Houk JANG ,  Haeryong KIM ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Donhee HAM

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.

公开(公告)号：US20220302319A1

公开(公告)日：2022-09-22

申请号：US17495457

申请日：2021-10-06

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Changseok LEE ,  Soonyong KWON ,  Junghwa KIM ,  Seungwoo SON ,  Seunguk SONG ,  Hyeonjin SHIN ,  Zonghoon LEE ,  Yeonchoo CHO

IPC: H01L29/786 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06

Abstract: Provided is a thin-film structure including a substrate, a nanocrystalline graphene layer provided on the substrate, and a two-dimensional material layer provided on the nanocrystalline graphene layer. The nucleation density of the two-dimensional material layer is 109 ea/cm2 or more according to the nanocrystalline graphene layer, and accordingly, a two-dimensional material layer having an improved uniformity may be formed and a time duration for forming the two-dimensional material layer may be greatly decreased.

公开(公告)号：US20220238692A1

公开(公告)日：2022-07-28

申请号：US17546303

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan NGUYEN ,  Minsu SEOL ,  Junyoung KWON ,  Hyeonjin SHIN ,  Minseok YOO ,  Yeonchoo CHO

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/304 ,  H01L21/463

Abstract: A method of patterning a 2D material layer is includes selectively forming a first material layer on a surface of a substrate to form a first region in which the first material layer covers the surface of the substrate and to further form a second region in which the surface of the substrate is exposed from the first material layer, the first material layer having a strong adhesive force with a 2D material. The method further includes forming a 2D material layer is formed in both the first region and the second region. The method further includes selectively removing the 2D material layer from the second region based on using a physical removal method, such that the 2D material layer remains in the first region.

公开(公告)号：US20220140100A1

公开(公告)日：2022-05-05

申请号：US17405619

申请日：2021-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonchoo CHO ,  Kyung-Eun BYUN ,  Hyeonjin SHIN

IPC: H01L29/45

Abstract: Disclosed is a semiconductor device including a surface-treated semiconductor layer. The semiconductor device includes a metal layer, a semiconductor layer electrically contacting the metal layer and having a surface treated with an element having an electron affinity of about 4 eV or greater, and a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure.

公开(公告)号：US20210327817A1

公开(公告)日：2021-10-21

申请号：US17362308

申请日：2021-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae SONG ,  Seunggeol NAM ,  Yeonchoo CHO ,  Seongjun PARK ,  Hyeonjin SHIN ,  Jaeho LEE

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US20210226011A1

公开(公告)日：2021-07-22

申请号：US16928508

申请日：2020-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423

Abstract: Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

公开(公告)号：US20210159183A1

公开(公告)日：2021-05-27

申请号：US17165246

申请日：2021-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun BYUN ,  Keunwook SHIN ,  Yonghoon KIM ,  Hyeonjin SHIN ,  Hyunjae SONG ,  Changseok LEE ,  Changhyun KIM ,  Yeonchoo CHO

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.