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    Memory devices with vertical channels
    31.
    发明授权
    Memory devices with vertical channels 有权

    公开(公告)号：US11508730B2

    公开(公告)日：2022-11-22

    申请号：US17032040

    申请日：2020-09-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Jaeho Hong

    IPC: H01L27/108 ,  G11C7/18

    Abstract: Memory devices may include a source region, channels, a gate insulation layer pattern, a selection gate pattern, a first gate pattern, a second gate pattern and a drain region. The source region may include first impurities having a first conductivity type at an upper portion of a substrate. The channels may contact the source region. Each of the channels may extend in a vertical direction that is perpendicular to an upper surface of the substrate. The selection gate pattern may be on sidewalls of the channels. The first gate pattern may be on the sidewalls of the channels. The first gate pattern may be a common electrode of all of multiple channels. The second gate patterns may be on the sidewalls of the channels. The drain region may include second impurities having a second conductivity type that is different from the first conductivity type at an upper portion of each of the channels.

    SEMICONDUCTOR MEMORY DEVICE
    32.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220199621A1

    公开(公告)日：2022-06-23

    申请号：US17541584

    申请日：2021-12-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Ilgweon Kim ,  Huijung Kim ,  Sungwon Yoo ,  Minhee Cho

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

    Semiconductor devices
    33.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11342436B2

    公开(公告)日：2022-05-24

    申请号：US16801508

    申请日：2020-02-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeho Hong ,  Yongseok Kim ,  Hyuncheol Kim ,  Seokhan Park ,  Satoru Yamada ,  Kyunghwan Lee

    IPC: H01L29/51 ,  H01L29/423 ,  H01L27/108 ,  H01L29/08

    Abstract: A semiconductor device includes a substrate including a recess, a first gate insulation layer on a lower sidewall and a bottom of the recess, the first gate insulation layer including an insulation material having hysteresis characteristics, a first gate electrode on the first gate insulation layer inside the recess, a second gate electrode contacting the first gate electrode in the recess, the second gate electrode including a material different from a material of the first gate electrode, and impurity regions on the substrate and adjacent to sidewalls of the recess, bottoms of the impurity regions being higher than a bottom of the second gate electrode relative to a bottom of the substrate.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    35.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200381448A1

    公开(公告)日：2020-12-03

    申请号：US16710198

    申请日：2019-12-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Kohji Kanamori ,  Minhan Shin

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

    Abstract: Three-dimensional semiconductor memory devices are provided. A three-dimensional semiconductor memory device includes a stack structure that includes gate electrodes on a substrate. The three-dimensional semiconductor memory device includes a first vertical structure, a second vertical structure, a third vertical structure, and a fourth vertical structure that penetrate the stack structure and are sequentially arranged in a zigzag shape along a first direction. Moreover, the three-dimensional semiconductor memory device includes a first bit line that extends in the first direction. The first bit line vertically overlaps the second vertical structure and the fourth vertical structure. Centers of the second and fourth vertical structures are spaced apart at the same distance from the first bit line. The first vertical structure is spaced apart at a first distance from the first bit line. The third vertical structure is spaced apart at a second distance from the first bit line.

    METHOD AND APPARATUS FOR CONTROLLING TRANSMISSION POWER OF TERMINAL IN MOBILE COMMUNICATION SYSTEM
    36.
    发明申请
    METHOD AND APPARATUS FOR CONTROLLING TRANSMISSION POWER OF TERMINAL IN MOBILE COMMUNICATION SYSTEM 审中-公开

    公开(公告)号：US20190053172A1

    公开(公告)日：2019-02-14

    申请号：US16100849

    申请日：2018-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongseok Kim ,  Hyunseok Ryu ,  Hyunkyu Yu

    IPC: H04W52/48 ,  H04W52/12 ,  H04W52/14

    Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services.A method for transmitting data by a terminal in a mobile communication system, a method for receiving data by a base station in a mobile communication system, a terminal in a mobile communication system, and a base station in a mobile communication system are provided. The method for transmitting data by a terminal in a mobile communication system includes receiving, from a base station, first control information for transmitting a first data; after receiving the first control information, receiving, from the base station, second control information for transmitting a second data; transmitting, to the base station, the second data corresponding to the second control information; and after transmitting the second data, determining a transmission power of the first data corresponding to the first control information based on a transmission power of the second data.

    SEMICONDUCTOR MEMORY DEVICE
    37.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230371265A1

    公开(公告)日：2023-11-16

    申请号：US18136993

    申请日：2023-04-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bongyong Lee ,  Myunghun Woo ,  Yongseok Kim

    IPC: H10B51/20 ,  H10B51/10 ,  H01L29/417 ,  H01L29/51

    CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L29/41725 ,  H01L29/516

    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a conductive layer on a substrate; an insulating isolation layer on the conductive layer; a stack structure on the insulating isolation layer, the stack structure including a plurality of source/drain contact layers and a plurality of gate electrode layers alternately provided along a first direction, perpendicular to an upper surface of the substrate; a vertical channel layer extending through the stack structure and the insulating isolation layer, wherein the vertical channel layer is in contact with each of the plurality of source/drain contact layers, and is connected to the conductive layer; and a gate insulating layer between each of the plurality of gate electrode layers and the vertical channel layer.

    Semiconductor Memory Device
    38.
    发明公开
    Semiconductor Memory Device 审中-公开

    公开(公告)号：US20230309317A1

    公开(公告)日：2023-09-28

    申请号：US18059010

    申请日：2022-11-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyuncheol KIM ,  Yongseok Kim ,  Kiheun Lee ,  Sangkil Lee ,  Daewon Ha

    IPC: H10B53/20 ,  H10B53/10 ,  H01L23/528

    CPC classification number: H01L27/11514 ,  H01L27/11504 ,  H01L23/5283

    Abstract: A semiconductor memory device is provided. The semiconductor memory device may include a semiconductor substrate; a data storage layer including capacitors disposed on the semiconductor substrate; a switching element layer on the data storage layer and including transistors connected to the respective capacitors; and a wiring layer on the switching element layer and including bit lines connected to the transistors, The respective transistors include an active pattern, a word line that crosses the active pattern such that the word line surrounds a first sidewall, a second sidewall and a top surface of the active pattern, and a ferroelectric layer between the word line and the active patter.

    SEMICONDUCTOR MEMORY DEVICE
    39.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230292490A1

    公开(公告)日：2023-09-14

    申请号：US18081905

    申请日：2022-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongjin Lee ,  Yongseok Kim ,  Mintae Ryu ,  Huije Ryu ,  Sungwon Yoo ,  Wonsok Lee ,  Minhee Cho

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/482

    Abstract: A semiconductor memory device includes a substrate, a conductive line extending in a first horizontal direction above the substrate, an isolation insulating layer including a channel trench extending in a second horizontal direction intersecting with the first horizontal direction and extending from an upper surface to a lower surface of the isolation insulating layer, above the conductive line, a channel structure disposed above the conductive line, a gate electrode extending in the second horizontal direction, in the channel trench, a capacitor structure above the isolation insulating layer, and a contact structure interposed between the channel structure and the capacitor structure, wherein the channel structure includes an amorphous oxide semiconductor layer disposed in the channel trench above the conductive line, and an upper crystalline oxide semiconductor layer interposed between the amorphous oxide semiconductor layer and the contact structure.

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