公开(公告)号：US10811109B2

公开(公告)日：2020-10-20

申请号：US16233723

申请日：2018-12-27

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Ching-Huang Lu ,  Vinh Diep ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C11/56

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

公开(公告)号：US10804282B2

公开(公告)日：2020-10-13

申请号：US16272468

申请日：2019-02-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Fei Zhou ,  Ching-Huang Lu ,  Raghuveer S. Makala

IPC: H01L27/11558 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11556

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and memory stack structures are formed through the alternating stack. A backside trench is formed through the alternating stack, and backside recesses are formed by removing the sacrificial material layers. An undoped aluminum oxide backside blocking dielectric layer is formed in the backside recesses and on sidewalls the backside trench. A portion of the undoped aluminum oxide backside blocking dielectric layer located at an upper end of the backside trench is converted into a carbon-doped aluminum oxide layer. An electrically conductive material is deposited in the backside recesses and at peripheral regions of the backside trench. The electrically conductive material at the peripheral regions of the backside trench is removed by an etch process, with the carbon-doped aluminum oxide layer providing etch resistivity during the etch process.

公开(公告)号：US20200312414A1

公开(公告)日：2020-10-01

申请号：US16900015

申请日：2020-06-12

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Ching-Huang Lu ,  Vinh Diep ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/24 ,  G11C16/10 ,  G11C11/56

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

公开(公告)号：US10665301B1

公开(公告)日：2020-05-26

申请号：US16245491

申请日：2019-01-11

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C11/56 ,  G11C16/26

Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.

公开(公告)号：US10121552B1

公开(公告)日：2018-11-06

申请号：US15495178

申请日：2017-04-24

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yingda Dong ,  Ching-Huang Lu ,  Nan Lu ,  Hong-Yan Chen

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C16/16 ,  G11C16/32 ,  G11C16/08

Abstract: A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.

公开(公告)号：US20180033798A1

公开(公告)日：2018-02-01

申请号：US15445409

申请日：2017-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Ching-Huang Lu ,  Yao-Sheng Lee ,  Jian Chen

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/28 ,  H01L23/532 ,  H01L27/11565 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/11565 ,  H01L29/40117 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.

公开(公告)号：US09812462B1

公开(公告)日：2017-11-07

申请号：US15175304

申请日：2016-06-07

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Ashish Baraskar ,  Yanli Zhang ,  Yingda Dong

IPC: H01L29/792 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7926

Abstract: Techniques are provided for fabricating a memory device in which the memory cells have a uniform program and erase speed. In one aspect, a memory device is provided with memory holes having diameters which become progressively smaller as a distance between the memory holes and a local interconnect become progressively larger. In another aspect, a fabrication process is provided for such a memory device. The memory holes which are relatively closer to the local interconnect have a relatively thinner blocking oxide layer due to etching used to remove a sacrificial material of the control gate layers. The increased diameter compensates for the thinner blocking oxide layer.

公开(公告)号：US09748266B1

公开(公告)日：2017-08-29

申请号：US15215080

申请日：2016-07-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Yanli Zhang ,  Liang Pang ,  Ching-Huang Lu ,  Matthias Baenninger ,  Yingda Dong

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/28282 ,  H01L27/1157

Abstract: A gate dielectric layer including a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer is formed on a horizontal semiconductor channel. An alternating stack of insulating layers and spacer material layers is formed over the gate dielectric layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conducive layers. Memory stack structures are formed through the alternating stack and the gate dielectric layer. Electrical charges can be injected into the charge trapping gate dielectric layer from the horizontal semiconductor channel to program the threshold voltage of a select field effect transistor employing a bottommost electrically conductive layer as a select gate electrode. The programmable threshold voltage can be advantageously employed to provide enhanced electrical isolation among word lines.