公开(公告)号：US11489043B2

公开(公告)日：2022-11-01

申请号：US16859196

申请日：2020-04-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Senaka Kanakamedala ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L29/06 ,  G11C8/14 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11519

Abstract: A three-dimensional memory device includes an alternating stack of word lines and at least one insulating layers or air gaps located over a substrate, a memory opening fill structure extending through the alternating stack. The memory opening fill structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The word lines are thicker than the insulating layers or air gaps.

公开(公告)号：US11043455B2

公开(公告)日：2021-06-22

申请号：US16519260

申请日：2019-07-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Johann Alsmeier ,  Jixin Yu

IPC: H01L23/535 ,  H01L27/11556 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11582

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. The vertically alternating sequence is divided into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches therethrough. Each neighboring pair of alternating stacks is laterally spaced apart from each other by a respective backside trench. The sacrificial material layers are replaced with multipart layers. Each multipart layer includes a respective electrically conductive layer that laterally extends continuously between a respective neighboring pair of backside trenches and at least one dielectric material plate that is a remaining portion of a sacrificial material layer, is laterally enclosed by the respective electrically conductive layer, and is laterally spaced from a most proximal one of the backside trenches by a uniform lateral offset distance.

公开(公告)号：US10985169B2

公开(公告)日：2021-04-20

申请号：US16291577

申请日：2019-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Murshed Chowdhury ,  Koichi Matsuno ,  Johann Alsmeier

IPC: H01L27/11556 ,  H01L23/538 ,  H01L27/11582 ,  H01L23/532 ,  H01L27/1157 ,  H01L23/00 ,  H01L25/18 ,  H01L23/498 ,  H01L27/11524

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

公开(公告)号：US10818685B2

公开(公告)日：2020-10-27

申请号：US16141163

申请日：2018-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mohan Dunga ,  James Kai ,  Venkatesh P. Ramachandra ,  Piyush Dak ,  Luisa Lin ,  Masaaki Higashitani

IPC: G11C11/24 ,  H01L27/11578 ,  G11C16/28 ,  G11C16/24 ,  H01L27/1157 ,  G11C16/08 ,  H01L27/11565 ,  H01L27/11573 ,  G11C16/30

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.

公开(公告)号：US10748927B1

公开(公告)日：2020-08-18

申请号：US16519092

申请日：2019-07-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Shigehisa Inoue ,  Tomohiro Kubo ,  James Kai

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11529

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, first memory opening fill structures extending through the alternating stack, where each of the first memory opening fill structures includes a respective first drain region, a respective first memory film, a respective first vertical semiconductor channel contacting an inner sidewall of the respective first memory film, and a respective first dielectric core, and a drain-select-level isolation structure having a pair of straight lengthwise sidewalls that extend along a first horizontal direction and contact straight sidewalls of the first memory opening fill structures. Each first vertical semiconductor channel includes a tubular section that underlies a horizontal plane including a bottom surface of the drain-select-level isolation structure and a semi-tubular section overlying the tubular section.

公开(公告)号：US10685978B1

公开(公告)日：2020-06-16

申请号：US16267592

申请日：2019-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ching-Huang Lu ,  Wei Zhao ,  Yanli Zhang ,  James Kai

IPC: H01L29/792 ,  H01L21/00 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: Electrical isolation between adjacent stripes of drain-select-level electrically conductive layers can be provided by forming a drain-select-level isolation structure between neighboring rows of memory stack structures. The drain-select-level isolation structure can partially cut through upper regions of the neighboring rows of memory stack structures. Vertical semiconductor channels of the neighboring rows of memory stack structures include a lower tubular segment and an upper semi-tubular segment that contact the drain-select-level isolation structure. Electrical current through drain select levels is limited to the semi-tubular segment of each vertical semiconductor channel. Alternatively, the drain-select-level isolation structure can be formed around the memory stack structures within the neighboring rows of memory stack structures. Ion implantation can be used to suppress conduction of electrical current through portions of vertical semiconductor channels that are proximal to the drain-select-level isolation structure.

公开(公告)号：US10559588B2

公开(公告)日：2020-02-11

申请号：US15971525

申请日：2018-05-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yingda Dong ,  Yangyin Chen ,  James Kai

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/02 ,  H01L29/20 ,  H01L27/06

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart among one another by line trenches and a two-dimensional array of memory stack structures and a two-dimensional array of dielectric pillar structures located in the line trenches. Each line trench is filled with laterally alternating sequence of memory stack structures and dielectric pillar structures. Each memory stack structure contains a vertical semiconductor channel, a pair of blocking dielectrics contacting outer sidewalls of the vertical semiconductor channel, a pair of charge storage layers contacting outer sidewalls of the pair of blocking dielectrics, and a pair of tunneling dielectrics contacting outer sidewalls of the pair of charge storage layers.

公开(公告)号：US20200013794A1

公开(公告)日：2020-01-09

申请号：US16141163

申请日：2018-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mohan Dunga ,  James Kai ,  Venkatesh P. Ramachandra ,  Piyush Dak ,  Luisa Lin ,  Masaaki Higashitani

IPC: H01L27/11578 ,  G11C16/28 ,  G11C11/24 ,  G11C16/24 ,  G11C16/30 ,  G11C16/08 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.

公开(公告)号：US10381443B2

公开(公告)日：2019-08-13

申请号：US15976442

申请日：2018-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuyo Matsumoto ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Hiroyuki Ogawa ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.

公开(公告)号：US20180233513A1

公开(公告)日：2018-08-16

申请号：US15948737

申请日：2018-04-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  James Kai ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/792 ,  G11C16/04 ,  G11C16/24

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/7926

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers. Vertical NAND strings are formed through the alternating stack, each of which includes a drain region, memory cell charge storage transistors, and a pair of drain select transistors in a series connection. A common bit line is electrically connected to drain regions of two vertical NAND strings. The drain select transistors of the two vertical NAND strings are configured such that drain select transistors sharing a first common drain select gate electrode provide a higher threshold voltage for one of the two vertical NAND strings, and drain select transistors sharing a second common drain select gate electrode provide a higher threshold voltage for the other of the two vertical NAND strings. The different threshold voltages can be provided by a combination of a masked ion implantation and selective charge injection.