公开(公告)号：US09087958B2

公开(公告)日：2015-07-21

申请号：US14600196

申请日：2015-01-20

申请人： Pengfei Wang ,  Xi Lin ,  Wei Wang ,  Xiaoyong Liu ,  Wei Zhang

发明人： Pengfei Wang ,  Xi Lin ,  Wei Wang ,  Xiaoyong Liu ,  Wei Zhang

IPC分类号： H01L27/30 ,  H01L31/111 ,  H01L31/0232 ,  H01L27/24 ,  H01L31/18 ,  H01L31/113

CPC分类号： H01L31/1804 ,  G02B6/42 ,  G02B6/4214 ,  H01L27/2454 ,  H01L27/304 ,  H01L31/02327 ,  H01L31/113 ,  H01L31/1136 ,  Y02E10/547 ,  Y02P70/521

摘要： The present invention belongs to the technical field of optical interconnection and relates to a photo detector, in particular to a photo detector consisting of tunneling field-effect transistors.

公开(公告)号：US08994095B2

公开(公告)日：2015-03-31

申请号：US13322640

申请日：2010-12-24

申请人： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

发明人： Pengfei Wang ,  Qingqing Sun ,  Shijin Ding ,  Wei Zhang

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L27/115

CPC分类号： H01L21/28273 ,  H01L27/11521

摘要： A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate (107); one drain region (108) of a first doping type; two source regions (101a, 101b) of a second doping type; and a stacked gate provided on the semiconductor substrate for capturing electrons. A memory array formed by a plurality of semiconductor memory devices and a manufacturing method thereof are also provided. The semiconductor memory device has the advantages of small cell area, simple manufacturing process and the like. The manufacturing cost of the memory device is reduced and the storing density of the memory device is increased.

摘要翻译： 提供了一种具有埋地漏极的半导体存储器件。 该器件包括半导体衬底（107）; 一个第一掺杂类型的漏极区域（108）; 具有第二掺杂类型的两个源极区域（101a，101b） 以及设置在半导体基板上用于捕获电子的堆叠栅极。 还提供了由多个半导体存储器件形成的存储器阵列及其制造方法。 半导体存储器件具有电池面积小，制造工艺简单等优点。 存储器件的制造成本降低，并且存储器件的存储密度增加。

公开(公告)号：US08966872B2

公开(公告)日：2015-03-03

申请号：US13991969

申请日：2011-11-15

申请人： Zhichao Cheng ,  Pengfei Wang ,  Jiankao Chen

发明人： Zhichao Cheng ,  Pengfei Wang ,  Jiankao Chen

IPC分类号： D07B1/06 ,  D07B7/02

CPC分类号： D07B1/0613 ,  D07B7/025 ,  D07B2201/2021 ,  D07B2201/2059 ,  D07B2201/2061 ,  D07B2501/2046 ,  D07B2501/2076 ,  Y10T428/1241 ,  D07B2801/14 ,  D07B2801/24

摘要： A steel cord (10) adapted for the reinforcement of elastomeric products comprises a core strand (12) and a layer of outer strands (14) arranged around the core strand (12). The core strand (12) comprises a core and at least a layer arranged around the core. The core further comprises one to three core filaments and the layer further comprises three to nine layer filaments. The core strand (12) has a first wave form and each filament of the outer strands (14) has a second wave form such that the first wave form is substantially different from the second wave form. This allows to guarantee full rubber penetration.

摘要翻译： 适于增强弹性体产品的钢丝帘线（10）包括芯线（12）和围绕芯股线（12）布置的外股线（14）层。 芯股线（12）包括芯部和至少围绕芯部布置的层。 核心还包括一至三根芯丝，并且该层还包含三至九层细丝。 芯股线（12）具有第一波形，并且外股线（14）的每个细丝具有第二波形，使得第一波形与第二波形基本不同。 这样可以保证橡胶的完全渗透。

公开(公告)号：US08932929B2

公开(公告)日：2015-01-13

申请号：US13812070

申请日：2012-04-24

申请人： Shijin Ding ,  Sun Chen ,  Xingmei Cui ,  Pengfei Wang ,  Wei Zhang

发明人： Shijin Ding ,  Sun Chen ,  Xingmei Cui ,  Pengfei Wang ,  Wei Zhang

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L29/66742 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： The invention relates to a thin film transistor memory and its fabricating method. This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown Al2O3 film. The charge storage layer is the two layer metal nanocrystals which include the first layer metal nanocrystals, the insulating layer and the second layer metal nanocrystals grown by ALD method in sequence from bottom to up. The charge tunneling layer is the symmetrical stack layer which includes the SiO2/HfO2/SiO2 or Al2O3/HfO2/Al2O3 film grown by ALD method in sequence from bottom to up. The active region of the device is the IGZO film grown by the RF sputtering method, and it is formed by the standard lithography and wet etch method. The TFT memory in this invention has the advantage with large P/E window, good data retention, high P/E speed, stable threshold voltage and simple fabricating process.

摘要翻译： 本发明涉及薄膜晶体管存储器及其制造方法。 从底部到顶部使用基板作为栅电极的这种存储器包括电荷阻挡层，电荷存储层，电荷隧道层，器件的有源区和源极/漏极。 电荷阻挡层是ALD生长的Al 2 O 3膜。 电荷存储层是包括第一层金属纳米晶体，绝缘层和第二层金属纳米晶体的两层金属纳米晶体，其由ALD方法依次从下到上生长。 电荷隧穿层是对称的堆叠层，其包括通过ALD法从下到上生长的SiO 2 / HfO 2 / SiO 2或Al 2 O 3 / HfO 2 / Al 2 O 3膜。 器件的有源区是通过RF溅射法生长的IGZO膜，并且通过标准光刻和湿蚀刻法形成。 本发明的TFT存储器具有P / E窗口大，数据保持性好，P / E速度高，阈值电压稳定，制造工艺简单的优点。

公开(公告)号：US08685788B2

公开(公告)日：2014-04-01

申请号：US13528398

申请日：2012-06-20

申请人： Weining Bao ,  Chengwei Cao ,  Pengfei Wang ,  Wei Zhang

发明人： Weining Bao ,  Chengwei Cao ,  Pengfei Wang ,  Wei Zhang

IPC分类号： H01L21/16

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  H01L29/0676 ,  H01L29/22 ,  H01L29/66356 ,  H01L29/7391

摘要： The present invention belongs to the technical field of semiconductor devices and specifically relates to a method for manufacturing a nanowire tunneling field effect transistor (TFET). In the method, the ZnO nanowire required is developed in a water bath without the need for high temperatures and high pressure, featuring a simple solution preparation, convenient development and low cost, as well as constituting MOS devices of vertical structure with nanowire directly, thus omitting the nanowire treatment in the subsequent stage. The present invention has the advantages of simple structure, convenient manufacturing, and low cost, and control of the nanowire channel developed and the MOSFET array with vertical structure made of it though the gate, so as to facilitate the manufacturing of large-scale MOSFET array directly.

摘要翻译： 本发明属于半导体器件的技术领域，具体涉及一种制造纳米线隧道场效应晶体管（TFET）的方法。 在该方法中，所需的ZnO纳米线在水浴中开发而不需要高温高压，具有简单的溶液制备，开发方便，成本低廉，并且直接构成具有纳米线的垂直结构的MOS器件，因此 在后续阶段省略纳米线治疗。 本发明结构简单，制造方便，成本低，纳米线通道的开发控制和栅极的垂直结构的MOSFET阵列，有利于大规模MOSFET阵列的制造 直。

公开(公告)号：US20130178014A1

公开(公告)日：2013-07-11

申请号：US13535032

申请日：2012-06-27

申请人： Pengfei Wang ,  Xiaoyong Liu ,  Qingqing Sun ,  Wei Zhang

发明人： Pengfei Wang ,  Xiaoyong Liu ,  Qingqing Sun ,  Wei Zhang

IPC分类号： H01L21/441

CPC分类号： H01L29/7391 ,  H01L29/8616

摘要： This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and a simple gate-control pn junction structure is configured; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through a floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed while the quantity of charges in the floating gate determines the device threshold voltage, thus realizing memory functions. This invention features capacity of manufacturing gate-control diode memory devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing. This invention is applicable to semiconductor devices manufacturing based on flexible substrate and flat panel displays and floating gate memories, etc.

摘要翻译： 本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体存储器件的方法。 当浮动栅极电压相对较高时，浮动栅极下的沟道为n型，并配置了简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过浮栅将n型ZnO反向为p型，并使用NiO作为p型半导体，形成npnp掺杂结构， 浮动门中的电荷决定了器件的阈值电压，从而实现了存储器的功能。 本发明具有制造栅极控制二极管存储器件的能力，其能够通过高驱动电流和小的次级阈值摆动的优点来降低芯片功耗。 本发明适用于基于柔性基板和平板显示器和浮动栅极存储器等的半导体器件制造。

公开(公告)号：US08455372B2

公开(公告)日：2013-06-04

申请号：US13528509

申请日：2012-06-20

申请人： Qingqing Sun ,  Runchen Fang ,  Wen Yang ,  Pengfei Wang ,  Wei Zhang

发明人： Qingqing Sun ,  Runchen Fang ,  Wen Yang ,  Pengfei Wang ,  Wei Zhang

IPC分类号： H01L21/31 ,  H01L21/00 ,  C30B28/06

CPC分类号： H01L21/0228 ,  H01L21/02052 ,  H01L21/02178 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/306

摘要： The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning and passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al2O3 dielectric. This method includes: use a new-type of sulfur passivant to react with the autologous oxide on the GaAs surface to clean it and generate a passive sulfide film to separate the GaAs from the outside environment, thus preventing the GaAs from oxidizing again; further cleaning the residuals such as autologous oxides and sulfides on the GaAs surface through the pretreatment reaction of the reaction source trimethyl aluminum (TMA) of the Al2O3 ALD with the GaAs surface, and then deposit high-quality Al2O3 dielectric through ALD as the gate dielectric which fully separates the GaAs from the outside environment. The present invention features a simple process and good effects, and can provide preconditions for manufacturing the GaAs devices.

摘要翻译： 本发明属于半导体材料的技术领域，具体涉及一种清洗和钝化砷化镓（GaAs）表面自氧化物并沉积Al2O3电介质的方法。 该方法包括：使用新型硫钝化剂与GaAs表面的自氧化物反应，对其进行清洗，并产生钝化的硫化物膜，使GaAs与外界环境分离，从而防止GaAs再次氧化; 通过Al2O3 ALD的反应物三甲基铝（TMA）与GaAs表面的预处理反应，进一步清洗GaAs表面上的残余物，如自生氧化物和硫化物，然后通过ALD作为栅极电介质沉积高质量的Al2O3电介质 其将GaAs与外部环境完全分离。 本发明具有简单的工艺和良好的效果，并且可以为制造GaAs器件提供前提条件。

公开(公告)号：US08426271B1

公开(公告)日：2013-04-23

申请号：US13534998

申请日：2012-06-27

申请人： Pengfei Wang ,  Chengwei Cao ,  Qingqing Sun ,  Wei Zhang

发明人： Pengfei Wang ,  Chengwei Cao ,  Qingqing Sun ,  Wei Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/7781 ,  H01L29/66825 ,  H01L29/788

摘要： This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and the device is of a simple gate-control pn junction structure; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The quantity of charges in the floating gate determines the device threshold voltage, thus realizing the memory functions. This invention features capacity of manufacturing memory devices able to reduce the chip power consumption through advantages of high driving current and small sub threshold swing, is applicable to semiconductor memory devices manufacturing based on flexible substrates and flat panel displays and floating gate memories, etc.

摘要翻译： 本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体存储器件的方法。 当浮动栅极电压相对较高时，浮动栅极下的沟道为n型，器件具有简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过浮栅将n型ZnO反转为p型，并使用NiO作为p型半导体，形成n-p-n-p掺杂结构。 浮栅中的电荷量决定了器件的阈值电压，从而实现了存储器的功能。 本发明特征在于能够通过高驱动电流和小次阈值摆动的优点来制造能够降低芯片功耗的存储器件的能力，可应用于基于柔性基板和平板显示器以及浮动栅极存储器等的半导体存储器件制造。

公开(公告)号：US20130092902A1

公开(公告)日：2013-04-18

申请号：US13528398

申请日：2012-06-20

申请人： Weining Bao ,  Chengwei Cao ,  Pengfei Wang ,  Wei Zhang

发明人： Weining Bao ,  Chengwei Cao ,  Pengfei Wang ,  Wei Zhang

IPC分类号： H01L29/78 ,  H01L21/336 ,  B82Y40/00

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  H01L29/0676 ,  H01L29/22 ,  H01L29/66356 ,  H01L29/7391

摘要： The present invention belongs to the technical field of semiconductor devices and specifically relates to a method for manufacturing a nanowire tunneling field effect transistor (TFET). In the method, the ZnO nanowire required is developed in a water bath without the need for high temperatures and high pressure, featuring a simple solution preparation, convenient development and low cost, as well as constituting MOS devices of vertical structure with nanowire directly, thus omitting the nanowire treatment in the subsequent stage. The present invention has the advantages of simple structure, convenient manufacturing, and low cost, and control of the nanowire channel developed and the MOSFET array with vertical structure made of it though the gate, so as to facilitate the manufacturing of large-scale MOSFET array directly.

摘要翻译： 本发明属于半导体器件的技术领域，具体涉及一种制造纳米线隧道场效应晶体管（TFET）的方法。 在该方法中，所需的ZnO纳米线在水浴中开发而不需要高温高压，具有简单的溶液制备，开发方便，成本低廉，并且直接构成具有纳米线的垂直结构的MOS器件，因此 在后续阶段省略纳米线治疗。 本发明结构简单，制造方便，成本低，纳米线通道的开发控制和栅极的垂直结构的MOSFET阵列，有利于大规模MOSFET阵列的制造 直。

公开(公告)号：US20130065365A1

公开(公告)日：2013-03-14

申请号：US13498144

申请日：2011-11-18

申请人： Pengfei Wang ,  Xi Lin ,  Wei Zhang

发明人： Pengfei Wang ,  Xi Lin ,  Wei Zhang

IPC分类号： H01L21/331

CPC分类号： H01L29/66333 ,  H01L21/76275 ,  H01L29/41741

摘要： The invention belongs to the technical field of high-voltage, large-power devices and in particular relates to a method for manufacturing a semiconductor substrate of a large-power device. According to the method, the ion implantation is carried out on the front face of a floating zone silicon wafer first, then a high-temperature resistant metal is used as a medium to bond the back-off floating zone silicon wafer, and a heavily CZ-doped silicon wafer forms the semiconductor substrate. After bonding, the floating zone silicon wafer is used to prepare an insulated gate bipolar transistor (IGBT), and the heavily CZ-doped silicon wafer is used as the low-resistance back contact, so the required amount of the floating zone silicon wafers used is reduced, and production cost is lowered. Meanwhile, the back metallization process is not required after bonding, so the processing procedures are simplified, and the production yield is enhanced.

摘要翻译： 本发明属于高压大功率器件的技术领域，特别涉及大功率器件的半导体衬底的制造方法。 根据该方法，首先在浮动区硅晶片的正面进行离子注入，然后使用耐高温金属作为介质来接合浮渣区硅晶片，并且重CZ 掺杂硅晶片形成半导体衬底。 在接合之后，使用浮动区硅晶片来制备绝缘栅双极晶体管（IGBT），并且将重CZ掺杂的硅晶片用作低电阻背接触，因此使用所需量的浮区硅晶片 降低了生产成本。 同时，接合后不需要背面金属化处理，因此简化了处理程序，并且提高了生产成品率。