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公开(公告)号：US08356216B2
公开(公告)日：2013-01-15
申请号：US13346538
申请日：2012-01-09
IPC分类号： G11C29/00
CPC分类号： G06F11/006 , G06F11/106
摘要： Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.
摘要翻译： 各种实施例包括当满足扫描条件时扫描存储器件的至少一部分以用于潜在错误的方法，装置和系统。 条件可以取决于多个读取操作，多个写入操作，时间等中的一个或多个。 公开了包括附加方法，装置和系统的其它实施例。
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32.发明申请MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS 有权存储器控制器，存储器系统，固态驱动器和处理多个命令的方法公开(公告)号：US20120324180A1
公开(公告)日：2012-12-20
申请号：US13599594
申请日：2012-08-30
IPC分类号： G06F12/00
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F3/0679 , G06F3/0688 , G06F13/161 , G06F13/28
摘要： The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
摘要翻译： 本公开包括用于存储器控制器的方法和装置。 在一个或多个实施例中，存储器控制器包括多个后端通道，以及通信地耦合到多个后端通道的命令队列。 命令队列配置为保存从主机接收的主机命令。 电路被配置为至少响应于命令队列中的主机命令的数量生成多个后端命令，并且将后端命令的数量分配给多个后端信道的数量。
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公开(公告)号：US20120311293A1
公开(公告)日：2012-12-06
申请号：US13118721
申请日：2011-05-31
申请人： Siamack Nemazie , Farshid Tabrizi , Berhanu Iman , Ruchir Shah , William E. Benson , Michael George
发明人： Siamack Nemazie , Farshid Tabrizi , Berhanu Iman , Ruchir Shah , William E. Benson , Michael George
IPC分类号： G06F12/02
CPC分类号： G06F12/0871 , G06F12/0246 , G06F12/0815 , G06F12/0893 , G06F2212/1016 , G06F2212/1032 , G06F2212/1044 , G06F2212/222 , G06F2212/224 , G06F2212/601 , G06F2212/6046 , G06F2212/621 , G06F2212/7203 , G06F2212/7206 , G11C11/5628 , G11C16/0483 , G11C16/06
摘要： Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.
摘要翻译： 公开了用于动态存储器高速缓存大小调整，启用动态存储器高速缓存大小调整，存储器件和存储器系统的方法。 用于动态存储器高速缓存大小调整的一种这样的方法确定存储器阵列中的可用存储器空间，并响应于可用存储器空间来调整存储器阵列中的存储器高速缓存的大小。
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公开(公告)号：US08266353B2
公开(公告)日：2012-09-11
申请号：US12404257
申请日：2009-03-13
IPC分类号： G06F3/00 , G06F5/00 , G06F13/12 , G06F13/38 , G01R31/08 , G01F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26
CPC分类号： G06F13/4022
摘要： An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.
摘要翻译： 本发明的实施例被公开为包括允许两个主机访问单端口SATA设备的SATA开关。还公开了用于减少SATA交换机的延迟和复杂性的实施例。
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35.发明申请公开(公告)号：US20120011335A1
公开(公告)日：2012-01-12
申请号：US13242535
申请日：2011-09-23
IPC分类号： G06F12/00
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F3/0679 , G06F3/0688 , G06F13/161 , G06F13/28
摘要： The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
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36.发明授权Memory controllers, memory systems, solid state drives and methods for processing a number of commands 有权存储器控制器，存储器系统，固态驱动器以及用于处理多个命令的方法公开(公告)号：US08055816B2
公开(公告)日：2011-11-08
申请号：US12421093
申请日：2009-04-09
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F3/0679 , G06F3/0688 , G06F13/161 , G06F13/28
摘要： The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
摘要翻译： 本公开包括用于存储器控制器的方法和装置。 在一个或多个实施例中，存储器控制器包括多个后端通道，以及通信地耦合到多个后端通道的命令队列。 命令队列配置为保存从主机接收的主机命令。 电路被配置为至少响应于命令队列中的主机命令的数量生成多个后端命令，并且将后端命令的数量分配给多个后端信道的数量。
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公开(公告)号：US20100313077A1
公开(公告)日：2010-12-09
申请号：US12846629
申请日：2010-07-29
IPC分类号： G06F11/26
CPC分类号： G06F11/006 , G06F11/106
摘要： Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.
摘要翻译： 各种实施例包括当满足扫描条件时扫描存储器件的至少一部分以用于潜在错误的方法，装置和系统。 条件可以取决于多个读取操作，多个写入操作，时间等中的一个或多个。 公开了包括附加方法，装置和系统的其它实施例。
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公开(公告)号：US20100228940A1
公开(公告)日：2010-09-09
申请号：US12397396
申请日：2009-03-04
申请人： Mehdi Asnaashari , Alan Chen , Siamack Nemazie
发明人： Mehdi Asnaashari , Alan Chen , Siamack Nemazie
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7209 , G11C29/76
摘要： Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective.
摘要翻译： 各种实施例包括具有组织成超块的物理块的至少两个平面的一个或多个存储器件，每个超级块包括来自至少两个平面中的每一个的物理块。 实施例包括确定平面内的有缺陷的块。 如果没有将特定块位置处的块都确定为有缺陷，则实施例包括将特定块位置处的块分配给超块，并且如果确定特定块位置处的一个或多个块被确定为有缺陷， 实施例包括：将确定为有缺陷的特定块位置的块分配给超块; 以及针对被确定为有缺陷的特定块位置处的所述一个或多个块中的每个块为所述超级块分配相应的替换块。 相应的替换块从包括被确定为有缺陷的相应块的平面中的相应一个中的多个块中选择。
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公开(公告)号：US20100211834A1
公开(公告)日：2010-08-19
申请号：US12388305
申请日：2009-02-18
CPC分类号： G06F11/1048 , G06F11/10 , G06F11/1004 , G06F13/28 , G06F21/64 , G11C2029/0411 , H03M13/09 , H03M13/13 , H03M13/29
摘要： The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.
摘要翻译： 本公开包括用于存储器控制器中的数据完整性的方法，设备和系统。 一个存储器控制器实施例包括耦合到主机接口的主机接口和第一错误检测电路。 存储器控制器可以包括耦合到存储器接口的存储器接口和第二错误检测电路。 第一错误检测电路可以被配置为计算从主机接口接收的数据的错误检测数据，并且检查发送到主机接口的数据的完整性。 第二错误检测电路可以被配置为计算发送到存储器接口的数据和第一纠错数据的纠错数据，并且检查数据的完整性和从存储器接口接收到的第一纠错数据。
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公开(公告)号：US5696775A
公开(公告)日：1997-12-09
申请号：US757074
申请日：1996-11-26
申请人： Siamack Nemazie , Son H. Ho , Ronald M. Yamada , Sunil Bhaskar Chaudhari , Christopher Paul Zook
发明人： Siamack Nemazie , Son H. Ho , Ronald M. Yamada , Sunil Bhaskar Chaudhari , Christopher Paul Zook
CPC分类号： G11B20/1833 , G11B27/3027 , G11B2220/20
摘要： A method and apparatus for detecting the transfer of a wrong sector uses the LBA to ensure that a correct sector is transferred. The LBA may be appended to the sector data during a write operation and verified during a read operation. Preferably, the LBA is embedded into the CRC block during a write operation and used to detect the transfer of a wrong sector during a read operation. The LBA may be embedded within the CRC, before or after it is transmitted to a CRC Generator/Checker, by Exclusive-ORing the sector data or CRC data with the LBA. During a read operation, the incoming CRC is Exclusive-ORed with the expected LBA of the sector being read, thereby eliminating the LBA from the CRC data. The CRC data is then checked by the CRC Generator/Checker and an error is signalled if the CRC data does not match. Using the method and apparatus of the present invention, the LBA may also be embedded in the CRC during format and minimal latency operations. Off-line sector identification is performed by extracting the LBA from the CRC for formats with and without an ID field.
摘要翻译： 用于检测错误扇区的传送的方法和装置使用LBA来确保正确的扇区被传送。 在写入操作期间，可以将LBA附加到扇区数据，并在读取操作期间进行验证。 优选地，LBA在写入操作期间嵌入到CRC块中，并且用于在读取操作期间检测错误扇区的传送。 通过将扇区数据或CRC数据与LBA进行异或运算，LBA可以嵌入到CRC内，在发送到CRC发生器/检查器之前或之后。 在读取操作期间，输入的CRC与被读取的扇区的期望的LBA进行异或运算，从而从CRC数据中消除LBA。 然后CRC校验器检查CRC数据，如果CRC数据不匹配则发出错误信号。 使用本发明的方法和装置，LBA也可以在格式化和最小等待时间操作期间嵌入到CRC中。 通过从具有和不具有ID字段的格式的CRC中提取LBA来执行离线扇区标识。
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