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    MAGNETIC RANDOM ACCESS MEMORY WITH DYNAMIC RANDOM ACCESS MEMORY (DRAM)-LIKE INTERFACE
    5.
    发明申请
    MAGNETIC RANDOM ACCESS MEMORY WITH DYNAMIC RANDOM ACCESS MEMORY (DRAM)-LIKE INTERFACE 有权
    具有动态随机存取存储器（DRAM）的磁性随机存取存储器 - 接口

    公开(公告)号：US20130073791A1

    公开(公告)日：2013-03-21

    申请号：US13303947

    申请日：2011-11-23

    申请人： Siamack Nemazie

    发明人： Siamack Nemazie

    IPC分类号： G06F12/00

    CPC分类号： G11C11/1675 ,  G06F12/0879 ,  G06F13/28 ,  G11C7/10 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693

    摘要： A memory device includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data, furthermore the memory device allowing burst write operation to begin while receiving data units of the next burst of data to be written or providing read data.

    摘要翻译： 存储器件包括用于在脉冲串写入操作期间存储数据突发的磁存储器单元，每个突发数据包括在每个数据单元以时钟周期接收的顺序数据单元，并且在突发写入操作期间写入， 写操作在多个时钟周期内执行。 此外，存储器件包括耦合到磁存储器单元的掩模寄存器，其在突发写入操作期间产生写掩码以禁止或启用写数据的数据单元，此外，存储器件允许突发写操作开始同时接收数据单元 要写入或提供读取数据的下一个数据组。

    Determining sector status in a memory device
    6.
    发明授权
    Determining sector status in a memory device 有权
    确定存储设备中的扇区状态

    公开(公告)号：US08276042B2

    公开(公告)日：2012-09-25

    申请号：US12364900

    申请日：2009-02-03

    申请人： Mehdi Asnaashari ,  Yu-Song Liao ,  Siamack Nemazie

    发明人： Mehdi Asnaashari ,  Yu-Song Liao ,  Siamack Nemazie

    IPC分类号： G06F11/00

    CPC分类号： G11C16/06 ,  G06F11/1012 ,  G11C29/04 ,  G11C2029/0411

    摘要： The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased.

    摘要翻译： 本公开包括用于操作半导体存储器的方法，设备，模块和系统。 许多方法实施例包括从对应于数据扇区的存储器单元读取数据，确定处于未擦除状态的存储单元的数量，以及如果未擦除状态的存储单元的数量小于 或等于可由ECC引擎校正的错误数量，确定扇区被擦除。

    Memory controllers, memory systems, solid state drives and methods for processing a number of commands
    7.
    发明授权
    Memory controllers, memory systems, solid state drives and methods for processing a number of commands 有权
    存储器控制器，存储器系统，固态驱动器以及用于处理多个命令的方法

    公开(公告)号：US08260973B2

    公开(公告)日：2012-09-04

    申请号：US13242535

    申请日：2011-09-23

    申请人： Mehdi Asnaashari ,  Yu-Song Liao ,  Jui-Yao Yang ,  Siamack Nemazie

    发明人： Mehdi Asnaashari ,  Yu-Song Liao ,  Jui-Yao Yang ,  Siamack Nemazie

    IPC分类号： G06F3/00 ,  G06F13/00

    CPC分类号： G06F3/061 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0679 ,  G06F3/0688 ,  G06F13/161 ,  G06F13/28

    摘要： The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

    摘要翻译： 本公开包括用于存储器控制器的方法和装置。 在一个或多个实施例中，存储器控制器包括多个后端通道，以及通信地耦合到多个后端通道的命令队列。 命令队列配置为保存从主机接收的主机命令。 电路被配置为至少响应于命令队列中的主机命令的数量生成多个后端命令，并且将后端命令的数量分配给多个后端信道的数量。

    EMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) BY MAGNETIC RANDOM ACCESS MEMORY (MRAM)
    9.
    发明申请
    EMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) BY MAGNETIC RANDOM ACCESS MEMORY (MRAM) 有权
    通过磁性随机存取存储器（MRAM）对静态随机存取存储器（SRAM）进行仿真

    公开(公告)号：US20120182795A1

    公开(公告)日：2012-07-19

    申请号：US13187402

    申请日：2011-07-20

    申请人： Petro Estakhri ,  Ebrahim Abedifard ,  Frederick Jaffin ,  Siamack Nemazie

    发明人： Petro Estakhri ,  Ebrahim Abedifard ,  Frederick Jaffin ,  Siamack Nemazie

    IPC分类号： G11C11/02

    CPC分类号： G11C11/1673 ,  G11C7/1042 ,  G11C8/04 ,  G11C11/1653 ,  G11C11/1675 ,  G11C11/1693

    摘要： A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.

    摘要翻译： 磁存储器系统包括包括多个磁存储器组的磁随机存取存储器（MRAM），并且可操作以在由写命令发起的写操作期间存储数据。 磁存储器系统还包括耦合到MRAM并且包括多个FIFO的先进先出（FIFO）接口设备。每个磁存储器组耦合到多个FIFO中的相应一个，FIFO是 可操作地在每个磁存储体的基础上排队写入命令，并进一步操作以在不使用MRAM时发出排队的写入命令，其中并行写入操作被执行到多个磁存储器组中的至少两个。

    Integrated disc drive controller
    10.
    发明授权
    Integrated disc drive controller 有权
    集成磁盘驱动器控制器

    公开(公告)号：US07475173B2

    公开(公告)日：2009-01-06

    申请号：US11378456

    申请日：2006-03-17

    申请人： Siamack Nemazie ,  Kaushik Popat ,  Balaji Virajpet ,  William R. Foland, Jr. ,  Roger McPherson ,  Maoxin Wei ,  Vineet Dujari ,  Shiang-Jyh Chang

    发明人： Siamack Nemazie ,  Kaushik Popat ,  Balaji Virajpet ,  William R. Foland, Jr. ,  Roger McPherson ,  Maoxin Wei ,  Vineet Dujari ,  Shiang-Jyh Chang

    IPC分类号： G06F13/00

    CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0673 ,  G06F3/0676 ,  G11B19/00 ,  G11B20/10009 ,  G11B25/043

    摘要： An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.

    摘要翻译： 集成数据存储控制系统在单一集成电路中提供RDC，伺服逻辑，ATA接口，微处理器以及其它以前分立的组件，在一个高度集成的系统设计中。 使用针对所有组件的单个集成电路技术类型（例如，数字CMOS）来呈现集成电路。 模拟和数字电路的组合方式是消除或减少模拟电路组件在数字电路中的噪声或干扰。 单个元件可以将它们的输出和输入多路复用在一起，使得各个元件可以选择性地切换（在测试模式期间），使得集成电路以与现有技术组件中的一个相同或相似的方式进行仿真或表现。 本发明可以应用于磁性硬盘驱动器（HDD）或诸如软盘控制器，光盘驱动器（例如CD-ROM等），磁带驱动器和其他数据存储设备的其它类型的存储设备。