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45 条记录 (耗时 0.032 秒)

    Composite barrier/etch stop layer comprising oxygen doped SiC and SiC for interconnect structures
    32.
    发明授权
    Composite barrier/etch stop layer comprising oxygen doped SiC and SiC for interconnect structures 有权
    复合阻挡层/蚀刻停止层，包括用于互连结构的掺杂氧的SiC和SiC

    公开(公告)号：US07538353B2

    公开(公告)日：2009-05-26

    申请号：US11410718

    申请日：2006-04-25

    申请人： Liu Huang ,  John Sudijono ,  Koh Yee Wee

    发明人： Liu Huang ,  John Sudijono ,  Koh Yee Wee

    IPC分类号： H01L29/15

    CPC分类号： H01L21/76835 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

    摘要： A dual damascene structure comprising a composite barrier/etch stop layer including a lower silicon carbide (SiC) layer and an upper first oxygen doped SiC layer formed over a substrate is provided. A first dielectric layer is formed over the first oxygen doped SiC layer followed by a second oxygen doped SiC etch stop layer, and a second dielectric layer. An opening with a via and an overlying trench extends through the second dielectric layer, the second oxygen doped SiC etch stop layer, the first dielectric layer, the upper first oxygen doped SiC layer and at least a portion of the lower silicon carbide (SiC) layer. The opening is filled with a diffusion barrier layer and a metal layer.

    摘要翻译： 提供了一种双镶嵌结构，其包括在衬底上形成的包括下碳化硅（SiC）层和上第一氧掺杂SiC层的复合势垒/蚀刻停止层。 第一介电层形成在第一氧掺杂的SiC层上，随后是第二氧掺杂的SiC蚀刻停止层和第二介电层。 具有通孔和覆盖沟槽的开口延伸穿过第二介电层，第二氧掺杂的SiC蚀刻停止层，第一介电层，上部第一氧化物掺杂的SiC层和至少一部分下部碳化硅（SiC） 层。 开口填充有扩散阻挡层和金属层。

    Composite stress spacer
    34.
    发明申请
    Composite stress spacer 有权
    复合应力间隔

    公开(公告)号：US20060252194A1

    公开(公告)日：2006-11-09

    申请号：US11122667

    申请日：2005-05-04

    申请人： Khee Lim ,  Wenhe Lin ,  Chung Lai ,  Yong Lee ,  Liang Hsia ,  Young Teh ,  John Sudijono ,  Wee Tan ,  Hui Koh

    发明人： Khee Lim ,  Wenhe Lin ,  Chung Lai ,  Yong Lee ,  Liang Hsia ,  Young Teh ,  John Sudijono ,  Wee Tan ,  Hui Koh

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823864

    摘要： An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.

    摘要翻译： 示例性方法实施例形成在PFET和NFET区域上在衬底上产生拉伸应力的间隔物。 我们形成PFET和NFET栅极，并在PFET和NFET栅极上形成拉伸间隔物。 我们将第一离子注入拉伸的PFET间隔物中以形成中和的应力PFET间隔物。 中和的应力PFET间隔物减轻了由衬底上的拉伸应力间隔物产生的拉伸应力。 这提高了设备​​性能。

    Use of amorphous carbon as a removable ARC material for dual damascene fabrication
    36.
    发明授权
    Use of amorphous carbon as a removable ARC material for dual damascene fabrication 失效
    使用无定形碳作为可拆卸的ARC材料进行双镶嵌制造

    公开(公告)号：US06787452B2

    公开(公告)日：2004-09-07

    申请号：US10290629

    申请日：2002-11-08

    申请人： John Sudijono ,  Liang Choo Hsia ,  Liu Huang

    发明人： John Sudijono ,  Liang Choo Hsia ,  Liu Huang

    IPC分类号： H01L214763

    CPC分类号： H01L21/76808 ,  H01L21/0276 ,  H01L21/31144 ,  H01L21/3146 ,  H01L21/76802 ,  Y10S438/952

    摘要： An improved method of controlling a critical dimension during a photoresist patterning process is provided which can be applied to forming vias and trenches in a dual damascene structure. An amorphous carbon ARC is deposited on a substrate by a PECVD method. Preferred conditions are a RF power from 50 to 500 Watts, a bias of 500 to 2000 Watts, a chamber and substrate temperature of 300° C. to 400° C. with a trimethylsilane flow rate of 50 to 200 sccm, a helium flow rate of 100 to 1000 sccm, and an argon flow rate of 50 to 200 sccm. Argon plasma imparts an amorphous character to the film. The refractive index (n and k) can be tuned for a variety of photoresist applications including 193 nm, 248 nm, and 365 nm exposures. The &agr;-carbon layer provides a high etch selectivity relative to oxide and can be easily removed with a plasma etch.

    摘要翻译： 提供了一种在光致抗蚀剂图案化工艺期间控制临界尺寸的改进方法，其可以应用于在双镶嵌结构中形成通路和沟槽。 通过PECVD方法将非晶碳ARC沉积在衬底上。 优选的条件是50至500瓦的RF功率，500至2000瓦特的偏压，室和基板温度为300℃至400℃，三甲基硅烷流速为50至200sccm，氦流量 为100〜1000sccm，氩气流量为50〜200sccm。 氩等离子体为电影赋予无定形特征。 折射率（n和k）可以针对各种光刻胶应用进行调整，包括193 nm，248 nm和365 nm曝光。 α碳层相对于氧化物提供高蚀刻选择性，并且可以容易地用等离子体蚀刻去除。

    Two-step, low argon, HDP CVD oxide deposition process
    37.
    发明授权
    Two-step, low argon, HDP CVD oxide deposition process 有权
    两步，低氩，HDP CVD氧化物沉积工艺

    公开(公告)号：US06211040B1

    公开(公告)日：2001-04-03

    申请号：US09398285

    申请日：1999-09-20

    申请人： Huang Liu ,  John Sudijono ,  Charles Lin ,  Quah Ya Lin

    发明人： Huang Liu ,  John Sudijono ,  Charles Lin ,  Quah Ya Lin

    IPC分类号： H01L2176

    CPC分类号： H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76224

    摘要： A method for depositing silicon dioxide between features has been achieved. The method may be applied intermetal dielectrics, interlevel dielectric, or shallow trench isolations. This method prevents dielectric voids, corner clipping, and plasma induced damage in very small feature applications. Features, such as conductive traces, are provided overlying a semiconductor substrate where the spaces between the features form gaps. A silicon dioxide liner layer is deposited overlying the features and lining the gaps, yet leaving the gaps open. The silicon dioxide liner layer depositing step is by high density plasma, chemical vapor deposition (HDP CVD) using a gas mixture comprising silane, oxygen, and argon. The argon gas pressure, chamber pressure, and the sputter rf energy are kept low. A silicon dioxide gap filling layer is deposited overlying the silicon dioxide liner layer to fill the gaps, and the integrated circuit device is completed. The silicon dioxide gap filling layer depositing step is by high density plasma, chemical vapor deposition (HDP CVD) using a gas mixture comprising silane, oxygen, and argon. The argon gas pressure and chamber pressure are kept low while the sputter rf energy is increased.

    摘要翻译： 已经实现了在特征之间沉积二氧化硅的方法。 该方法可以应用金属间电介质，层间电介质或浅沟槽隔离。 该方法在非常小的特征应用中防止电介质空隙，拐角限制和等离子体引起的损坏。 提供诸如导电迹线的特征覆盖在半导体衬底上，其中特征之间的空隙形成间隙。 沉积二氧化硅衬垫层覆盖特征并衬里间隙，但留下间隙打开。 二氧化硅衬层沉积步骤是使用包含硅烷，氧和氩的气体混合物的高密度等离子体，化学气相沉积（HDP CVD）。 氩气压力，室压力和溅射能量保持较低。 沉积二氧化硅间隙填充层，覆盖二氧化硅衬垫层以填充间隙，并且完成集成电路器件。 二氧化硅间隙填充层沉积步骤是使用包含硅烷，氧和氩的气体混合物的高密度等离子体化学气相沉积（HDP CVD）。 氩气压力和室压力保持较低，同时溅射能量增加。

    Polishing method with inert gas injection
    39.
    发明授权
    Polishing method with inert gas injection 有权
    惰性气体注入抛光方法

    公开(公告)号：US08143166B2

    公开(公告)日：2012-03-27

    申请号：US12046151

    申请日：2008-03-11

    申请人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

    发明人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

    IPC分类号： H01L21/461

    CPC分类号： H01L21/31053 ,  H01L21/3212

    摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.

    摘要翻译： 在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。 在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。 惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。 增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。 抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。