公开(公告)号：US20090061873A1

公开(公告)日：2009-03-05

申请号：US11896355

申请日：2007-08-31

申请人： Derek Hongwei Bao ,  David Chiang

发明人： Derek Hongwei Bao ,  David Chiang

IPC分类号： H04Q7/20

CPC分类号： H04W36/22 ,  H04W16/32 ,  H04W36/38 ,  H04W84/045

摘要： A femto cell at a customer premises, such as an IP-based femto Base Transceiver System (IP-BTS), can be configured as a “private access” node intended to service a limited set of mobile stations. However, mobile stations not associated with the private femto cell may acquire and lock onto the femto BTS. To avoid service blockages in such cases, the private femto BTS will allow call access attempts by, and call deliveries to, a non-associated mobile station, despite the “private access” configuration. However, upon completion of call set-up, the non-associated mobile station is directed to initiate handoff, from the private femto cell coverage provided by the femto BTS into a cell coverage of a base station of the macro network, to conserve femto cell resources for use in servicing calls of the associated mobile station(s).

摘要翻译： 诸如基于IP的毫微微基站收发器系统（IP-BTS）之类的客户驻地的毫微微小区可被配置为旨在服务有限的一组移动站的“专用接入”节点。 然而，与私有毫微微小区无关的移动站可以获取并锁定到毫微微BTS。 为了避免在这种情况下的服务阻塞，私人毫微微BTS将允许呼叫接入尝试，并且呼叫非接入移动台的传送，尽管有“私有接入”配置。 然而，在完成呼叫建立之后，非关联移动台被指示从毫微微BTS提供的私人毫微微小区覆盖范围开始到宏网络的基站的小区覆盖范围内的切换，以节省毫微微小区 用于维护相关移动台的呼叫的资源。

公开(公告)号：US07464088B1

公开(公告)日：2008-12-09

申请号：US10846174

申请日：2004-05-13

申请人： David Chiang

发明人： David Chiang

IPC分类号： G06F7/00 ,  G06F12/00

CPC分类号： G06F17/30985 ,  Y10S707/99933 ,  Y10S707/99936

摘要： A system architecture optimized for pattern match applications is provided. This system architecture includes a host computer and a pattern match accelerator (PMA), which in turn includes one or more pattern match units (PMUs) and PMU control logic. The PMU control logic can divide a database, transmitted by the host computer, such that each of the PMUs receives a database portion. Each PMU includes a main memory for storing the database portion and a programmable logic device (PLD). The PLD can perform a search and score operation on its database portion. Advantageously, the PLD can be configured to generate an index of the database portion, and then configured to perform the search and score operation using that index. The PMU control logic can assemble the results of the pattern match application from each of the PMUs.

摘要翻译： 提供了针对模式匹配应用优化的系统架构。 该系统架构包括主计算机和模式匹配加速器（PMA），其继而包括一个或多个模式匹配单元（PMU）和PMU控制逻辑。 PMU控制逻辑可以划分由主计算机发送的数据库，使得每个PMU接收数据库部分。 每个PMU包括用于存储数据库部分的主存储器和可编程逻辑器件（PLD）。 PLD可以在其数据库部分执行搜索和分数操作。 有利地，PLD可以被配置为生成数据库部分的索引，然后被配置为使用该索引执行搜索和分数操作。 PMU控制逻辑可以从每个PMU组合模式匹配应用的结果。

公开(公告)号：US20060000129A1

公开(公告)日：2006-01-05

申请号：US10884755

申请日：2004-07-02

申请人： David Chiang

发明人： David Chiang

IPC分类号： G09F13/26

CPC分类号： G09F13/26

摘要： A neon sign arrangement includes a supporting frame, a displaying cover, and a neon light unit. The supporting frame has a first displaying side and an opposed second displaying side. The displaying cover has a displaying character mounted on the first displaying side. The neon light unit includes a neon light tube which has a character sign portion and is supported by the supporting frame, and a power controller which is electrically connected to the neon light tube such that when it is powered up, it forms as a light source to highlight the displaying cover as well as generate a neon light effect at the second displaying side.

摘要翻译： 霓虹灯排列包括支撑框架，显示罩和霓虹灯单元。 支撑框架具有第一显示侧和相对的第二显示侧。 显示盖具有安装在第一显示侧的显示字符。 霓虹灯单元包括具有字符符号部分并由支撑框架支撑的氖灯管和电连接到氖灯管的功率控制器，使得当其被加电时，其形成为光源 突出显示屏幕，并在第二显示侧产生霓虹灯效果。

公开(公告)号：US06255845B1

公开(公告)日：2001-07-03

申请号：US09495477

申请日：2000-02-01

申请人： Jacques Wong ,  David Chiang ,  Jaime Tolentino

发明人： Jacques Wong ,  David Chiang ,  Jaime Tolentino

IPC分类号： H03K19173

CPC分类号： H03K19/1736

摘要： A spare gate cell on a integrated circuit contains both a configurable logic gate and one or more inverters. Inputs of these circuits have an appearance, accessible by the automatic place-and-route tool, at the topmost metal layer on the integrated circuit, which is metal 3 or higher. The outputs of the circuit preferably are accessible up to the same metal layer. The combination of the configurable gate circuit and one or more inverters enables any one such cell to selectively implement a wide range of logic functions by making appropriate connections during fib-mill processing of the integrated circuit device. The use of interconnections at the topmost layer facilitates reconfiguring a circuit to implement desired logic and interconnection thereof into the pre-defined logic on the integrated circuit. The inventive spare gate cells provide a high degree of design flexibility, both for circuit debug operations and for implementation of enhanced logic functions.

摘要翻译： 集成电路上的备用栅极单元包含可配置逻辑门和一个或多个反相器。 这些电路的输入通过自动布线工具可以在金属3或更高的集成电路的最顶层的金属层上具有外观。 电路的输出优选地可访问到相同的金属层。 可配置门电路和一个或多个逆变器的组合使得任何一个这样的单元能够通过在集成电路器件的纤维磨加工期间进行适当的连接来选择性地实现广泛的逻辑功能。 在最上层使用互连有助于重新配置电路以实现期望的逻辑及其互连到集成电路中的预定逻辑。 本发明的备用栅极单元为电路调试操作和实现增强的逻辑功能提供高度的设计灵活性。

公开(公告)号：US06172519B2

公开(公告)日：2001-01-09

申请号：US08993596

申请日：1997-12-18

申请人： David Chiang ,  Jesse H. Jenkins, IV ,  Robert A. Olah

发明人： David Chiang ,  Jesse H. Jenkins, IV ,  Robert A. Olah

IPC分类号： H03K19173

CPC分类号： H03K19/17772 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17744 ,  H03K19/17764 ,  H03K19/1778

摘要： A method of operating a pin of an in-system programmable logic device (ISPLD) which includes the steps of (1) applying a predetermined voltage to the pin when the ISPLD is in a set-up mode, and (2) maintaining the last voltage applied to the pin when the ISPLD is in a normal operating mode. The ISPLD is in the set-up mode when the logic of the ISPLD has not yet been configured, or is being configured. The ISPLD is in the normal operating mode after the logic of the ISPLD has been configured. A particular ISPLD includes a pin and a logic gate having a first input terminal coupled to the pin, a second input terminal coupled to receive a control signal, and an output terminal coupled to the pin. When the ISPLD is in the set-up mode, the control signal causes the logic gate to apply a predetermined voltage to the pin. When the ISPLD is in the normal operating mode, the control signal causes the logic gate to maintain the last applied voltage on the pin.

摘要翻译： 一种操作系统可编程逻辑器件（ISPLD）的引脚的方法，其包括以下步骤：（1）当ISPLD处于建立模式时，向引脚施加预定电压，以及（2）保持最后一个 当ISPLD处于正常工作模式时，施加到引脚的电压。 当ISPLD的逻辑尚未配置或正在配置时，ISPLD处于设置模式。 在ISPLD的逻辑配置完成后，ISPLD处于正常工作模式。 特定的ISPLD包括引脚和逻辑门，其具有耦合到引脚的第一输入端，耦合以接收控制信号的第二输入端，以及耦合到引脚的输出端。 当ISPLD处于建立模式时，控制信号使逻辑门对引脚施加预定的电压。 当ISPLD处于正常工作模式时，控制信号使逻辑门保持引脚上的最后施加电压。

公开(公告)号：US5764076A

公开(公告)日：1998-06-09

申请号：US670472

申请日：1996-06-26

申请人： Napoleon W. Lee ,  Derek R. Curd ,  Jeffrey H. Seltzer ,  Jeffrey Goldberg ,  David Chiang ,  Kameswara K. Rao ,  Nicholas Kucharewski, Jr.

发明人： Napoleon W. Lee ,  Derek R. Curd ,  Jeffrey H. Seltzer ,  Jeffrey Goldberg ,  David Chiang ,  Kameswara K. Rao ,  Nicholas Kucharewski, Jr.

IPC分类号： G06F17/50 ,  H03K19/177

CPC分类号： H03K19/17752 ,  G06F17/5054 ,  H03K19/17704 ,  H03K19/17756

摘要： A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic functions. The PLD also includes an instruction-blocking circuit that is connected to each of the functional blocks. When directed by a user, the instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions. Thus, one or more function blocks in the PLD are reprogrammed without interrupting the operation of the remaining function blocks.

摘要翻译： 一种复杂的可编程逻辑器件（PLD），包括多个可编程功能块和用于接收编程指令的指令总线。 编程指令用于对功能块进行编程，以使PLD能够执行一个或多个所需的逻辑功能。 PLD还包括连接到每个功能块的指令阻塞电路。 当用户指示时，指令分块电路有选择地阻止来自一个或多个功能块的指令总线上的编程指令，同时允许其他功能块接收编程指令。 因此，PLD中的一个或多个功能块被重新编程，而不中断剩余功能块的操作。

公开(公告)号：US5506878A

公开(公告)日：1996-04-09

申请号：US277382

申请日：1994-07-18

申请人： David Chiang

发明人： David Chiang

IPC分类号： H03K5/00 ,  H03K5/135 ,  H03K5/156 ,  H03K21/08

CPC分类号： H03K5/135 ,  H03K5/00006 ,  H03K5/156

摘要： An input clock delay circuit includes an up counter for estimating the approximate number of internal clock cycles that occur during one cycle of the input clock signal and another up counter for determining the portion of each cycle of the input clock signal that is high. A clock manipulation circuit receives each counter's value, and may be set to perform a fixed transform on the input clock signal, such as clock delay/advance, duty cycle shifting, and frequency multiplication/division. The clock manipulation circuit output values are loaded into two down counters that are also clocked by the internal clock. On the rising edge of the input clock signal, the first down counter starts decrementing until the counter reaches zero, indicating that the desired delay interval has passed, at which point the delayed output clock signal is taken high. The second down counter then starts decrementing for an interval that is equal to the desired duty cycle of the output clock signal. When the second down counter reaches zero, the output clock signal is taken low, and the process repeats.

摘要翻译： 输入时钟延迟电路包括用于估计在输入时钟信号的一个周期期间发生的内部时钟周期的近似数量的向上计数器，以及用于确定输入时钟信号的每个周期的部分高的另一个上计数器。 时钟控制电路接收每个计数器的值，并且可以设置为对输入时钟信号执行固定变换，例如时钟延迟/提前，占空比移位和倍频/除法。 时钟控制电路的输出值被加载到也由内部时钟计时的两个向下计数器中。 在输入时钟信号的上升沿，第一个递减计数器开始递减，直到计数器达到零，表示所需的延迟时间间隔已过，此时延迟的输出时钟信号变为高电平。 然后，第二递减计数器开始递减等于输出时钟信号的期望占空比的间隔。 当第二个递减计数器达到零时，输出时钟信号变为低电平，重复该过程。

公开(公告)号：US5506523A

公开(公告)日：1996-04-09

申请号：US204717

申请日：1994-03-01

申请人： David Chiang ,  Nicholas Kucharewski, Jr.

发明人： David Chiang ,  Nicholas Kucharewski, Jr.

IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C16/28 ,  H03K19/00 ,  G11C7/00

CPC分类号： H03K19/0016 ,  G11C16/0441 ,  G11C16/26 ,  G11C16/28

摘要： The present invention provides a sense circuit including a first bit line, a second bit line, a first plurality of memory cells coupled to the first bit line, a second plurality of memory cells coupled to the second bit line, and selection circuitry coupled to the first bit line and the second bit line. The selection circuitry provides a wide AND gate function in one mode and provides a zero power circuit for generating a function of a single input in another mode.

摘要翻译： 本发明提供了一种感测电路，其包括第一位线，第二位线，耦合到第一位线的第一多个存储器单元，耦合到第二位线的第二多个存储单元，以及耦合到第二位线的选择电路 第一位线和第二位线。 选择电路在一种模式下提供宽的与门功能，并且提供用于在另一模式中产生单个输入的功能的零功率电路。

公开(公告)号：US5448181A

公开(公告)日：1995-09-05

申请号：US310203

申请日：1994-09-20

申请人： David Chiang

发明人： David Chiang

IPC分类号： H03K19/003 ,  H03K19/094 ,  H03K17/16 ,  H03K19/0948

CPC分类号： H03K19/09429 ,  H03K19/00361

摘要： A CMOS or NMOS output buffer equalizes the number of logic gates in the signal paths connected to both the pull up and pull down transistors. In one embodiment, the pull down transistor signal path includes the conventional inverter connected to the output of a NAND gate. The pull up transistor signal path includes a CMOS passgate including two transistors connected together controlled by the output enable signal and passing the output data signal to a conventional output inverter stage. Also an additional transistor controlled by the output enable signal provides an additional signal to the input of the pull up transistor output inverter stage when the output enable signal is low. The provision of balanced signal paths in terms of number of gates and therefore propagation time to both the pull up and pull down transistors evens out the rise and fall crowbar switching current and thus minimizes switching noise.

摘要翻译： CMOS或NMOS输出缓冲器均衡连接到上拉和下拉晶体管的信号路径中的逻辑门数。 在一个实施例中，下拉晶体管信号路径包括连接到NAND门的输出的常规反相器。 上拉晶体管信号路径包括CMOS通道，其包括由输出使能信号连接在一起的两个晶体管，并将输出数据信号传递到常规的输出反相器级。 另外，当输出使能信号为低电平时，由输出使能信号控制的附加晶体管也向上拉晶体管输出反相器级的输入端提供附加信号。 根据门数量提供平衡信号路径，从而提供上拉和下拉晶体管的传播时间，可以提高和降低撬棒开关电流，从而最大限度地减少开关噪声。

公开(公告)号：US5349249A

公开(公告)日：1994-09-20

申请号：US43882

申请日：1993-04-07

申请人： David Chiang ,  Thomas Y. Ho ,  Wei-Yi Ku ,  George H. Simmons ,  Robert W. Barker

发明人： David Chiang ,  Thomas Y. Ho ,  Wei-Yi Ku ,  George H. Simmons ,  Robert W. Barker

IPC分类号： G06F12/14 ,  G06F21/79 ,  H03K19/177 ,  H04L9/10 ,  H04L9/00

CPC分类号： H01L23/57 ,  G06F12/1425 ,  G06F21/79 ,  H01L2924/0002

摘要： More than one security bit is used in a block of a PLD chip. The internal configuration and other information is left unprotected when all the security bits are in the erased state, and is protected by programming one or all the security bits. The security bits are located physically in proximity to the areas containing configuration and any other user-defined data, both so that they are difficult to discover and so that the erasure of all security bits in a EPROM-based PLD would cause a large number of adjacent user-defined bits to be erased as well, hence making it very difficult to extract useful information from a protected device by reverse engineering. Situating security bits in a different, pseudorandom location within each block of the chip makes them difficult to find and so further inhibits reverse engineering.

摘要翻译： 在PLD芯片的一个块中使用了多个安全位。 当所有安全位都处于擦除状态时，内部配置和其他信息将不受保护，并通过编程一个或所有安全位进行保护。 安全位在物理上位于包含配置和任何其他用户定义的数据的区域附近，这两者都难以发现，并且使得基于EPROM的PLD中所有安全位的擦除将导致大量 相邻的用户定义的位也被擦除，因此通过逆向工程从受保护的设备中提取有用的信息非常困难。 在芯片的每个块内的不同的伪随机位置将安全位置于状态，使得它们难以找到，因此进一步禁止逆向工程。