公开(公告)号：US07592665B2

公开(公告)日：2009-09-22

申请号：US11594327

申请日：2006-11-08

申请人： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

发明人： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.

摘要翻译： 非易失性存储器件可以包括具有单元区域的衬底和在衬底的单元区域上的单元器件隔离层，以限定电池活性区域。 浮置栅极可以包括顺序堆叠在单元有源区上的下浮置栅极和上浮置栅极，并且隧道绝缘图案可以在浮栅和电池有源区之间。 控制栅极电极可以在浮置栅极上，并且阻挡绝缘图案可以在控制栅电极和浮栅之间。 更具体地说，上部浮动栅极可以包括在下部浮动栅极上的平坦部分和从邻近电池器件隔离层的平坦部分的两个边缘向上延伸的一对壁部分。 此外，由平坦部分和一对壁部分围绕的空间的上部的宽度可以大于空间的下部的宽度。 还讨论了相关方法。

公开(公告)号：US07449763B2

公开(公告)日：2008-11-11

申请号：US11530827

申请日：2006-09-11

申请人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  Y10S257/905

摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.

摘要翻译： 本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。 非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。 每个器件隔离层具有突出在半导体衬底上的侧壁。 多个字线跨越器件隔离层。 隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。 浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。 形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极 顺序堆叠的图案。 然后在器件隔离层和控制栅极图案上形成导电层。 此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

公开(公告)号：US20070066003A1

公开(公告)日：2007-03-22

申请号：US11558634

申请日：2006-11-10

申请人： Sung-Hoi Hur ,  Jung-Dal Choi

发明人： Sung-Hoi Hur ,  Jung-Dal Choi

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.

摘要翻译： 半导体存储器件包括其中具有沟槽的半导体衬底。 第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。 在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。 分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。 在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。 还讨论了相关方法。

公开(公告)号：US20070048922A1

公开(公告)日：2007-03-01

申请号：US11509007

申请日：2006-08-24

申请人： Ji-Hwon Lee ,  Sung-Hoi Hur

发明人： Ji-Hwon Lee ,  Sung-Hoi Hur

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.

摘要翻译： NAND包括设置在限定多个有源区的衬底的区域中的器件隔离图案。 具有构成单元串的存储器栅极图案的存储晶体管跨过多个有源区。 选择晶体管设置在存储晶体管的上方，并且下部插头设置在单元串的每一侧，以电连接单元串和选择晶体管的两侧上的多个有源区。

公开(公告)号：US07018894B2

公开(公告)日：2006-03-28

申请号：US10891803

申请日：2004-07-14

申请人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

发明人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

摘要： An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

摘要翻译： EEPROM包括用于限定多个有源区的器件隔离层，跨越有源区延伸的一对控制栅极和跨越有源区延伸并插入在控制栅极图案之间的一对选择栅极图案。 浮动栅极图案形成在跨越有源区域的控制栅极图案延伸的交叉区域上。 在选择栅极图案跨越有源区域延伸的交叉区域上形成下部栅极图案。 栅极间电介质图案设置在控制栅极图案和浮置栅极图案之间，并且虚设电介质图案设置在选择栅极图案和下部栅极图案之间。 虚拟介质图案基本上平行于选择栅极图案，并且与选择栅极图案的一个侧壁自对准以重叠选择栅极图案的预定宽度。

公开(公告)号：US20060033166A1

公开(公告)日：2006-02-16

申请号：US11020311

申请日：2004-12-22

申请人： Min-Cheol Park ,  Sung-Hoi Hur

发明人： Min-Cheol Park ,  Sung-Hoi Hur

IPC分类号： H01L29/94

CPC分类号： H01L21/76877 ,  H01L21/28525 ,  H01L29/66628 ,  H01L29/78

摘要： Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second impurity doped regions, and first and second holes may be formed in the insulating layer, with the first and second holes respectively exposing portions of the first and second impurity doped regions. In addition, first and second epitaxial semiconductor layers may be formed in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate. Related devices are also discussed.

摘要翻译： 形成电子器件的方法可以包括在半导体衬底上形成栅电极，以及在栅电极的相对侧上形成半导体衬底的第一和第二杂质掺杂区。 可以在包括第一和第二杂质掺杂区域的半导体衬底上形成绝缘层，并且可以在绝缘层中形成第一和第二孔，其中第一和第二孔分别暴露第一和第二杂质掺杂区域的部分。 此外，可以在半导体衬底的第一和第二杂质掺杂区域的暴露部分上的相应的第一和第二孔中形成第一和第二外延半导体层。 还讨论了相关设备。

公开(公告)号：US20050152176A1

公开(公告)日：2005-07-14

申请号：US11048852

申请日：2005-02-03

申请人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/115 ,  G11C11/24

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954

摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

公开(公告)号：US06559029B2

公开(公告)日：2003-05-06

申请号：US10174896

申请日：2002-06-17

申请人： Sung-Hoi Hur

发明人： Sung-Hoi Hur

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： The present invention provides a method of fabricating a semiconductor device having a trench isolation structure. The method includes the following steps. A hard mask layer is formed on the semiconductor substrate having a cell array region and a peripheral circuit region. The hard mask layer is patterned to expose the semiconductor substrate. Thus, a hard mask pattern is formed to define a first isolation region at the cell array region and simultaneously to define a second isolation region at the peripheral circuit region. A sacrificial material layer is conformally formed at the entire surface of the second isolation region and the hard mask pattern of the peripheral circuit region and fills a gap region between the hard mask patterns of the cell array region. The sacrificial material layer and the semiconductor substrate are sequentially etched to form a first trench region and a second trench region at the cell array region and the peripheral circuit region, respectively. The first trench region is shallower than the second trench region.

公开(公告)号：US06376876B1

公开(公告)日：2002-04-23

申请号：US09678917

申请日：2000-10-04

申请人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur

发明人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur

IPC分类号： H01L2978

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

摘要翻译： 提供了NAND​​型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。 该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。 源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。 源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

公开(公告)号：US20120223379A1

公开(公告)日：2012-09-06

申请号：US13407187

申请日：2012-02-28

申请人： Hyun-Sil OH ,  Sung-Hoi Hur ,  Dae-Sin Kim

发明人： Hyun-Sil OH ,  Sung-Hoi Hur ,  Dae-Sin Kim

IPC分类号： H01L27/105 ,  H01L21/762

CPC分类号： H01L27/11521 ,  G11C16/0466

摘要： A non-volatile memory device includes a substrate including a plurality of active regions and a plurality of device isolating trenches formed between a respective one of each of the active regions along a first direction in the substrate. A plurality of gate structures each including a tunnel insulating layer pattern, a floating gate electrode, a dielectric layer pattern and a control gate electrode is formed on the substrate. A first insulating layer pattern is provided within the device isolating trenches. A second insulating layer pattern is formed along an inner surface portion of a gap between the gate structures. An impurity doped polysilicon pattern is formed on the second insulating layer pattern in the gap between the gate structures.

摘要翻译： 非易失性存储器件包括：衬底，其包括多个有源区和多个器件隔离沟槽，沿着衬底中的第一方向形成在每个有源区中的相应一个之间。 在衬底上形成各自包括隧道绝缘层图案，浮栅电极，电介质层图案和控制栅极电极的多个栅极结构。 在器件隔离沟槽内提供第一绝缘层图案。 沿着栅极结构之间的间隙的内表面部分形成第二绝缘层图案。 在栅极结构之间的间隙中的第二绝缘层图案上形成杂质掺杂多晶硅图案。