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102 条记录 (耗时 0.044 秒)

    Method and apparatus for selectively compacting test reponses
    32.
    发明申请
    Method and apparatus for selectively compacting test reponses 有权
    用于选择性压实测试报告的方法和设备

    公开(公告)号：US20050097419A1

    公开(公告)日：2005-05-05

    申请号：US10973522

    申请日：2004-10-25

    申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

    发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L21/822 ,  H01L27/04 ,  G06F11/00

    CPC分类号： G01R31/318547

    摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

    摘要翻译： 一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。 所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。 在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。 该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。 第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。 第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。 其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

    Method and apparatus for selectively compacting test responses
    33.
    发明授权
    Method and apparatus for selectively compacting test responses 有权
    用于选择性压实测试响应的方法和装置

    公开(公告)号：US06829740B2

    公开(公告)日：2004-12-07

    申请号：US10354576

    申请日：2003-01-29

    申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

    发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

    IPC分类号： G01R3128

    CPC分类号： G01R31/318547

    摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

    摘要翻译： 一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。 所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。 在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。 该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。 第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。 第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。 其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

    Bist architecture for detecting path-delay faults in a sequential circuit
    34.
    发明授权
    Bist architecture for detecting path-delay faults in a sequential circuit 失效
    用于检测顺序电路中的路径延迟故障的Bist架构

    公开(公告)号：US6148425A

    公开(公告)日：2000-11-14

    申请号：US22759

    申请日：1998-02-12

    申请人： Sudipta Bhawmik ,  Tapan Jyoti Chakraborty ,  Nilanjan Mukherjee

    发明人： Sudipta Bhawmik ,  Tapan Jyoti Chakraborty ,  Nilanjan Mukherjee

    IPC分类号： G01R31/30 ,  G01R31/3185 ,  G01R31/28

    CPC分类号： G01R31/3016 ,  G01R31/31858

    摘要： A scan-based BIST architecture for detecting path-delay faults in a sequential circuit converted to a combinational circuit or a less complex sequential circuit including a combinational portion and a plurality of scan flip-flops. The BIST structure includes a test pattern generator for generating two test patterns and a controller for generating a clock signal and an extended scan mode signal which is held high for two clock cycles while the output response of the combinational portion to the first and second test vectors is latched into the scan flip-flops in order to detect a signal transition. The invention is further directed to a method for detection of path-delay faults using this scan-based BIST architecture. To improve the fault coverage for path-delay faults, observation points may be inserted at the inputs of selected scan flip-flops. A predetermined number of scan flip-flops having the highest activation frequency are selected as the observation points.

    摘要翻译： 一种基于扫描的BIST架构，用于检测转换到组合电路的顺序电路中的路径延迟故障或包括组合部分和多个扫描触发器的较不复杂的时序电路。 BIST结构包括用于产生两个测试模式的测试模式发生器和用于产生时钟信号的控制器和用于两个时钟周期保持高电平的扩展扫描模式信号，同时组合部分对第一和第二测试向量的输出响应 被锁存到扫描触发器中以便检测信号转换。 本发明还涉及一种使用该基于扫描的BIST架构来检测路径延迟故障的方法。 为了改善路径延迟故障的故障覆盖范围，可以在所选择的扫描触发器的输入端插入观察点。 选择具有最高激活频率的预定数量的扫描触发器作为观察点。

    Test scheduling with pattern-independent test access mechanism
    35.
    发明授权
    Test scheduling with pattern-independent test access mechanism 有权
    测试调度与模式无关的测试访问机制

    公开(公告)号：US09088522B2

    公开(公告)日：2015-07-21

    申请号：US13980287

    申请日：2012-01-17

    申请人： Janusz Rajski ,  Mark A Kassab ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Jakub Janicki ,  Jerzy Tyszer ,  Avijit Dutta

    发明人： Janusz Rajski ,  Mark A Kassab ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Jakub Janicki ,  Jerzy Tyszer ,  Avijit Dutta

    IPC分类号： H04L12/26 ,  G01R31/3183 ,  G06F11/263

    CPC分类号： H04L43/50 ,  G01R31/318335 ,  G06F11/263

    摘要： Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.

    摘要翻译： 公开了用于在电路系统中测试多个核的测试调度的方法，装置和系统的代表性实施例。 编码测试数据以导出需要少量核心输入通道的压缩测试模式。 相应地确定每个压缩测试图案的核心输入/输出通道要求信息。 压缩的模式被分组成测试模式类。 测试模式类的形成之后是分配电路输入和输出通道以及测试应用时隙，其可以包括将互补测试模式类合并成可以与特定测试访问机制一起工作的集群。 可以独立于测试数据设计测试访问机制。

    Selective per-cycle masking of scan chains for system level test
    37.
    发明授权
    Selective per-cycle masking of scan chains for system level test 有权
    用于系统级测试的扫描链选择性每周期屏蔽

    公开(公告)号：US08726113B2

    公开(公告)日：2014-05-13

    申请号：US13453929

    申请日：2012-04-23

    申请人： Janusz Rajski ,  Dariusz Czysz ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Jerzy Tyszer

    发明人： Janusz Rajski ,  Dariusz Czysz ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Jerzy Tyszer

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31703 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/318547 ,  G06F11/27

    摘要： Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.

    摘要翻译： 用于处理未知状态问题的集成电路的内置自检技术。 一些实现使用与时间压缩器相连的专用扫描链选择器。 专门的扫描链选择器的存在提高了掩蔽X状态的效率。 还公开了：（1）与多个扫描链和时间压实器一起工作的选择器的架构，（2）用于确定和编码随后抑制X状态的每个周期扫描链选择掩模的方法，以及（3） 以处理过度掩蔽现象。

    On-chip comparison and response collection tools and techniques
    38.
    发明授权
    On-chip comparison and response collection tools and techniques 有权
    片上比较和响应收集工具和技术

    公开(公告)号：US08418007B2

    公开(公告)日：2013-04-09

    申请号：US13053188

    申请日：2011-03-21

    申请人： Nilanjan Mukherjee ,  Janusz Rajski ,  Jerzy Tyszer

    发明人： Nilanjan Mukherjee ,  Janusz Rajski ,  Jerzy Tyszer

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318547 ,  G01R31/318563 ,  G01R31/318566

    摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000x. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

    摘要翻译： 这里公开了所谓的X压测试响应压实机的示例性实施例。 所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。 所公开技术的某些实施例提供约1000x的压实比。 所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。 扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。 本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。