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公开(公告)号：US11011567B2
公开(公告)日：2021-05-18
申请号：US16678425
申请日：2019-11-08
Inventor： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Feng-Chi Hung , Shuang-Ji Tsai , Jeng-Shyan Lin , Shu-Ting Tsai , Wen-I Hsu
IPC: H01L31/00 , H01L27/146 , H01L31/02
Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
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公开(公告)号：US20200075659A1
公开(公告)日：2020-03-05
申请号：US16678425
申请日：2019-11-08
Inventor： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Feng-Chi Hung , Shuang-Ji Tsai , Jen-Shyan Lin , Shu-Ting Tsai , Wen-I Hsu
IPC: H01L27/146 , H01L31/02
Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
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公开(公告)号：US10157959B2
公开(公告)日：2018-12-18
申请号：US15864979
申请日：2018-01-08
Inventor： Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung , Tzu-Hsuan Hsu , Shu-Ting Tsai , Min-Feng Kao
IPC: H01L21/768 , H01L27/146 , H01L23/48
Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
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公开(公告)号：US09666630B2
公开(公告)日：2017-05-30
申请号：US15066658
申请日：2016-03-10
Inventor： Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Tzu-Hsuan Hsu , Feng-Chi Hung , Min-Feng Kao
IPC: H01L27/146
CPC classification number: H01L27/14636 , H01L27/14603 , H01L27/1463 , H01L27/14632 , H01L27/14634 , H01L27/1464 , H01L27/14687 , H01L27/1469
Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.
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公开(公告)号：US09666566B1
公开(公告)日：2017-05-30
申请号：US15138993
申请日：2016-04-26
Inventor： Ju-Shi Chen , Cheng-Ying Ho , Chun-Chieh Chuang , Sheng-Chau Chen , Shih Pei Chou , Hui-Wen Shen , Dun-Nian Yaung , Ching-Chun Wang , Feng-Chi Hung , Shyh-Fann Ting
CPC classification number: H01L25/105 , H01L25/50 , H01L2225/1041 , H01L2225/1082
Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 Å. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may also be employed to promote topographic uniformity at wafer edges. Improved planarity of wafers presented for hybrid bonding results in improved bond uniformity for 3DIC devices formed thereby.
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Patent Agency Ranking
公开(公告)号：US09570503B2
公开(公告)日：2017-02-14
申请号：US14660605
申请日：2015-03-17
Inventor： Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Keng-Yu Chou , Pao-Tung Chen , Wen-De Wang
IPC: H01L31/0232 , H01L27/146
CPC classification number: H01L27/14685 , H01L27/1462 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/1464 , H01L27/14643 , H01L27/14689
Abstract: Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor includes first and second radiation-detection devices that are disposed in the substrate. The first and second radiation-detection devices are operable to detect radiation waves that enter the substrate through the back side. The image sensor also includes an anti-reflective coating (ARC) layer. The ARC layer is disposed over the back side of the substrate. The ARC layer has first and second ridges that are disposed over the first and second radiation-detection devices, respectively. The first and second ridges each have a first refractive index value. The first and second ridges are separated by a substance having a second refractive index value that is less than the first refractive index value.
Abstract translation: 提供了一种图像传感器装置。 图像传感器装置包括具有正面和背面的基板。 图像传感器包括设置在基板中的第一和第二放射线检测装置。 第一和第二放射线检测装置可操作以检测通过背面进入衬底的辐射波。 图像传感器还包括抗反射涂层（ARC）层。 ARC层设置在基板的背面上。 ARC层具有分别设置在第一和第二辐射检测装置上的第一和第二脊。 第一和第二脊各自具有第一折射率值。 第一和第二脊由具有小于第一折射率值的第二折射率值的物质分开。
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公开(公告)号：US09559244B2
公开(公告)日：2017-01-31
申请号：US14725480
申请日：2015-05-29
Inventor： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Hsiao-Hui Tseng , Tzu-Hsuan Hsu
IPC: H01L31/18 , H01L31/02 , H01L31/103 , H01L27/146
CPC classification number: H01L31/18 , H01L27/1461 , H01L27/14621 , H01L27/14627 , H01L27/1464 , H01L27/14689 , H01L31/02 , H01L31/103 , H01L31/1804 , Y02E10/547 , Y02P70/521
Abstract: A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate. A surface layer of the semiconductor substrate is implanted to form a third doped region of an opposite conductivity type than the first and the second doped regions. The third doped region forms a diode with the first and the second doped regions.
Abstract translation: 一种方法包括形成包括第一开口的第一注入掩模，通过第一开口注入半导体衬底的第一部分以形成第一掺杂区，形成包括第二开口的第二注入掩模，以及注入半导体的第二部分 衬底以形成第二掺杂区域。 半导体衬底的第一部分被半导体衬底的第二部分包围。 注入半导体衬底的表面层以形成与第一和第二掺杂区相反导电类型的第三掺杂区。 第三掺杂区域形成具有第一和第二掺杂区域的二极管。
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公开(公告)号：US09373657B2
公开(公告)日：2016-06-21
申请号：US14163060
申请日：2014-01-24
Inventor： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang
IPC: H01L27/146
CPC classification number: H01L27/14634 , H01L27/1464 , H01L27/14643 , H01L27/14689 , H01L27/1469 , H01L27/14696
Abstract: A system and method for fabricating a 3D image sensor structure is disclosed. The method comprises providing an image sensor with a backside illuminated photosensitive region on a substrate, applying a first dielectric layer to the first side of the substrate opposite the substrate side where image data is gathered, and applying a semiconductor layer that is optionally polysilicon, to the first dielectric layer. A least one control transistor may be created on the first dielectric layer, within the semiconductor layer and may optionally be a row select, reset or source follower transistor. An intermetal dielectric may be applied over the first dielectric layer; and may have at least one metal interconnect disposed therein. A second interlevel dielectric layer may be disposed on the control transistors. The dielectric layers and semiconductor layer may be applied by bonding a wafer to the substrate or via deposition.
Abstract translation: 公开了一种用于制造3D图像传感器结构的系统和方法。 该方法包括在基板上提供具有背面照射感光区域的图像传感器，将第一电介质层施加到与图像数据收集的基板侧相对的基板的第一侧，以及施加可选择的多晶硅的半导体层， 第一介电层。 可以在半导体层内的第一介电层上形成至少一个控制晶体管，并且可以可选地是行选择，复位或源极跟随器晶体管。 可以在第一介电层上施加金属间电介质; 并且可以具有布置在其中的至少一个金属互连。 第二层间电介质层可以设置在控制晶体管上。 电介质层和半导体层可以通过将晶片结合到衬底或通过沉积来施加。
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公开(公告)号：US09147703B2
公开(公告)日：2015-09-29
申请号：US14057140
申请日：2013-10-18
Inventor： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Wen-De Wang
IPC: H01L31/14 , H01L27/146
CPC classification number: H01L27/146 , H01L27/14632 , H01L27/14636 , H01L27/1464 , H01L27/14687
Abstract: Provided is a method of fabricating an image sensor device. The method includes providing a first substrate having a radiation-sensing region disposed therein. The method includes providing a second substrate having a hydrogen implant layer, the hydrogen implant layer dividing the second substrate into a first portion and a second portion. The method includes bonding the first portion of the second substrate to the first substrate. The method includes after the bonding, removing the second portion of the second substrate. The method includes after the removing, forming one or more microelectronic devices in the first portion of the second substrate. The method includes forming an interconnect structure over the first portion of the second substrate, the interconnect structure containing interconnect features that are electrically coupled to the microelectronic devices.
Abstract translation: 提供了一种制造图像传感器装置的方法。 该方法包括提供其中设置有辐射感测区域的第一基板。 该方法包括提供具有氢注入层的第二衬底，氢注入层将第二衬底分成第一部分和第二部分。 该方法包括将第二衬底的第一部分接合到第一衬底。 该方法包括在接合之后，去除第二衬底的第二部分。 该方法包括在去除之后，在第二衬底的第一部分中形成一个或多个微电子器件。 该方法包括在第二基板的第一部分上形成互连结构，所述互连结构包含电耦合到微电子器件的互连特征。
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公开(公告)号：US20150179613A1
公开(公告)日：2015-06-25
申请号：US14135153
申请日：2013-12-19
Inventor： Shu-Ting Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Chia-Chieh Lin , U-Ting Chen
IPC: H01L25/065 , H01L23/48 , H01L25/00 , H01L21/768 , H01L23/528 , H01L23/532
CPC classification number: H01L25/0657 , H01L21/76805 , H01L21/76831 , H01L21/76898 , H01L23/481 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L24/80 , H01L24/82 , H01L24/92 , H01L25/50 , H01L2224/24145 , H01L2224/80896 , H01L2224/82106 , H01L2224/9202 , H01L2224/9212 , H01L2225/06541 , H01L2924/0002 , H01L2924/00 , H05K3/467 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
Abstract translation: 提供了互连装置和形成互连装置的方法。 两个集成电路结合在一起。 通过一个基板形成第一开口。 沿着第一开口的侧壁和底部形成多层电介质膜。 形成从第一开口延伸到集成电路中的焊盘的第二开口。 形成电介质衬垫，并且用导电材料填充开口以形成导电插塞。
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