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公开(公告)号：US11907633B2
公开(公告)日：2024-02-20
申请号：US17818417
申请日：2022-08-09
Inventor： Cheok-Kei Lei , Yu-Chi Li , Chia-Wei Tseng , Zhe-Wei Jiang , Chi-Lin Liu , Jerry Chang-Jui Kao , Jung-Chan Yang , Chi-Yu Lu , Hui-Zhong Zhuang
IPC: G06F30/392 , G06F30/394 , G06F30/398
CPC classification number: G06F30/392 , G06F30/394 , G06F30/398
Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.
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公开(公告)号：US11853670B2
公开(公告)日：2023-12-26
申请号：US17525173
申请日：2021-11-12
Inventor： Chih-Yu Lai , Chih-Liang Chen , Chi-Yu Lu , Shang-Hsuan Chiu
IPC: G06F30/39 , H01L29/40 , G06F30/392 , G06F30/398 , G06F30/394
CPC classification number: G06F30/39 , G06F30/392 , G06F30/394 , G06F30/398 , H01L29/401
Abstract: An integrated circuit includes a first conductor segment intersecting a first active-region structure at a source/drain region and a second conductor segment intersecting a second active-region structure at a source/drain region. The first conductor segment and the second conductor segment are separated at proximal edges by a separation distance. The first conductor has a distal edge separated from a first power rail, and the second conductor segment is connected to a second power rail through a via-connector. A distance from the first power rail to a proximal edge of the first conductor segment is larger than a distance from the second power rail to a proximal edge of the second conductor segment by a predetermined distance that is a fraction of the separation distance.
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公开(公告)号：US11842131B2
公开(公告)日：2023-12-12
申请号：US17222057
申请日：2021-04-05
Inventor： Mao-Wei Chiu , Ting-Wei Chiang , Hui-Zhong Zhuang , Li-Chun Tien , Chi-Yu Lu
IPC: G06F30/30 , G06F30/39 , G06F30/392 , G06F30/394 , G06F30/398 , G06F115/08 , H01L23/528 , H01L27/02
CPC classification number: G06F30/30 , G06F30/39 , G06F30/392 , G06F30/394 , G06F30/398 , G06F2115/08 , H01L23/528 , H01L27/0207
Abstract: A method for manufacturing a semiconductor device to which corresponds a layout diagram stored on a non-transitory computer-readable medium. The method includes generating the layout diagram using an electronic design system (EDS), the EDS including at least one processor and at least one memory including computer program code for one or more programs are configured to cause the EDS to execute the generating. Testing the semiconductor device. Revising, the layout diagram, based on testing results indicative of selected standard functional cells in the layout diagram which merit modification or replacement. Programming one or more of the ECO cells which correspond to the one or more selected standard functional cells resulting in one or more programmed ECO cells. Routing the one or more programmed ECO cells correspondingly to at least one of the selected standard functional cells or to one or more other ones of the standard functional cells.
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公开(公告)号：US11775727B2
公开(公告)日：2023-10-03
申请号：US16299973
申请日：2019-03-12
Inventor： Fong-Yuan Chang , Chin-Chou Liu , Hui-Zhong Zhuang , Meng-Kai Hsu , Pin-Dai Sue , Po-Hsiang Huang , Yi-Kan Cheng , Chi-Yu Lu , Jung-Chou Tsai
IPC: G06F30/398 , G06F30/392 , G06F30/394 , G06F119/18
CPC classification number: G06F30/398 , G06F30/392 , G06F30/394 , G06F2119/18
Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
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公开(公告)号：US11764213B2
公开(公告)日：2023-09-19
申请号：US17214194
申请日：2021-03-26
Inventor： Chih-Yu Lai , Chih-Liang Chen , Chi-Yu Lu , Shang-Syuan Ciou , Hui-Zhong Zhuang , Ching-Wei Tsai , Shang-Wen Chang
IPC: H01L27/06 , G06F30/394 , H01L23/528 , H01L29/06 , H01L29/423 , H01L29/417 , H01L29/786 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8234 , H01L29/66 , G06F30/392 , H01L23/48
CPC classification number: H01L27/0694 , G06F30/392 , G06F30/394 , H01L21/0259 , H01L21/76898 , H01L21/8221 , H01L21/823412 , H01L21/823475 , H01L23/481 , H01L23/5283 , H01L29/0665 , H01L29/41733 , H01L29/42392 , H01L29/66742 , H01L29/78696
Abstract: A semiconductor device includes a substrate and a first active region on a first side of the substrate. The semiconductor device further includes a first gate structure surrounding a first portion of the first active region. The semiconductor device further includes a second active region on a second side of the substrate, wherein the second side is opposite the first side. The semiconductor device further includes a second gate structure surrounding a first portion of the second active region. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.
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Patent Agency Ranking
公开(公告)号：US20230281373A1
公开(公告)日：2023-09-07
申请号：US17856412
申请日：2022-07-01
Inventor： Shang-Hsuan Chiu , Chih-Liang Chen , Hui-Zhong Zhuang , Chi-Yu Lu , Jerry Chang Jui Kao
IPC: G06F30/392
CPC classification number: G06F30/392 , G06F2119/18
Abstract: Metallization structure for an integrated circuit. In one embodiment, an integrated circuit includes a metal-to-diffusion (MD) layer disposed over an active region of a cell, gates disposed over the active region of the cell, and a first metallization layer including M0 tracks disposed over the MD layer and the gates. The integrated circuit further includes a second metallization layer including M1 tracks disposed over the first metallization layer. The M1 tracks include first M1 tracks each having a first predetermined distance from an edge of the cell and second M1 tracks each having a second predetermined distance from the edge of the cell, wherein the first MI tracks are longer than the second M1 tracks.
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公开(公告)号：US11574110B2
公开(公告)日：2023-02-07
申请号：US16206960
申请日：2018-11-30
Inventor： Jung-Chan Yang , Ting-Wei Chiang , Jerry Chang-Jui Kao , Hui-Zhong Zhuang , Lee-Chung Lu , Li-Chun Tien , Meng-Hung Shen , Shang-Chih Hsieh , Chi-Yu Lu
IPC: G06F30/394 , H01L27/118 , H01L23/522 , H01L23/528 , H01L27/02
Abstract: A method of fabricating an integrated circuit structure includes placing a first set of conductive structure layout patterns on a first layout level, placing a second set of conductive structure layout patterns on a second layout level, placing a first set of via layout patterns between the second set of conductive structure layout patterns and the first set of conductive structure layout patterns, and manufacturing the integrated circuit structure based on at least one of the layout patterns of the integrated circuit. At least one of the layout patterns is stored on a non-transitory computer-readable medium, and at least one of the placing operations is performed by a hardware processor. The first set of conductive structure layout patterns extends in a first direction. The second set of conductive structure layout patterns extends in the second direction, and overlap the first set of conductive structure layout patterns.
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公开(公告)号：US11494543B2
公开(公告)日：2022-11-08
申请号：US16883575
申请日：2020-05-26
Inventor： Cheok-Kei Lei , Yu-Chi Li , Chia-Wei Tseng , Zhe-Wei Jiang , Chi-Lin Liu , Jerry Chang-Jui Kao , Jung-Chan Yang , Chi-Yu Lu , Hui-Zhong Zhuang
IPC: G06F30/392 , G06F30/394 , G06F30/398
Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.
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公开(公告)号：US11461528B2
公开(公告)日：2022-10-04
申请号：US16908288
申请日：2020-06-22
Inventor： Jung-Chan Yang , Ting-Wei Chiang , Jerry Chang-Jui Kao , Hui-Zhong Zhuang , Lee-Chung Lu , Li-Chun Tien , Meng-Hung Shen , Shang-Chih Hsieh , Chi-Yu Lu
IPC: G06F30/394 , H01L23/522 , H01L27/118 , H01L23/528 , H01L27/02
Abstract: An integrated circuit structure includes a first, a second and a third set of conductive structures and a first and a second set of vias. The first set of conductive structures extend in a first direction, and is located at a first level. The second set of conductive structures extends in a second direction, overlaps the first set of conductive structures, and is located at a second level. The first set of vias is between, and electrically couples the first and the second set of conductive structures. The third set of conductive structures extends in the first direction, overlaps the second set of conductive structures, covers a portion of the first set of conductive structures, and is located at a third level. The second set of vias is between, and electrically couples the second and the third set of conductive structures.
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公开(公告)号：US11030372B2
公开(公告)日：2021-06-08
申请号：US16659351
申请日：2019-10-21
Inventor： Pin-Dai Sue , Chin-Chou Liu , Sheng-Hsiung Chen , Fong-Yuan Chang , Lee-Chung Lu , Yen-Hung Lin , Li-Chun Tien , Po-Hsiang Huang , Yi-Kan Cheng , Chi-Yu Lu
IPC: G06F30/00 , G06F30/392 , G06F30/394 , G06F111/20
Abstract: A method (of generating a layout diagram) includes generating a cell, representing at least part of a circuit in a semiconductor device, which is arranged at least in part according to second tracks of the M_2nd level (M_2nd tracks), and first tracks of the M_1st level (M_1st tracks). The generating the cell includes: selecting, based on a chosen site for the cell in the layout diagram, one of the M_2nd tracks; generating a first M_2nd pin pattern representing an output pin of the circuit; arranging a long axis of the first pin pattern substantially along the selected M_2nd track; generating second, third, fourth and fifth M_1st pin patterns representing corresponding input pins of the circuit; and arranging long axes of the second to fifth pin patterns substantially along corresponding ones of the M_1st tracks.
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