Semiconductor structure and method for forming the same

    公开(公告)号:US11940662B2

    公开(公告)日:2024-03-26

    申请号:US17081763

    申请日:2020-10-27

    IPC分类号: G02B6/42 G02B6/43

    摘要: The semiconductor structure includes a die, a dielectric layer surrounding the die, a photoelectric device disposed adjacent to the die and surrounded by the dielectric layer, a first opening extending through the redistribution layer and configured to receive a light-conducting member, and a metallic shield extending at least partially through the redistribution layer and surrounding the first opening. A method for forming a semiconductor structure includes receiving a die; forming a dielectric layer to surround the die; and disposing a photoelectric device surrounded by the dielectric layer; forming a redistribution layer over the die, the dielectric layer and the photoelectric device; and removing a portion of the redistribution layer to form a first opening over the photoelectric device. A metallic shield extending at least partially through the redistribution layer and surrounding the first opening is formed during the formation of the redistribution layer.

    VERTICALLY MOUNTED DIE GROUPS
    34.
    发明公开

    公开(公告)号:US20240014172A1

    公开(公告)日:2024-01-11

    申请号:US18473273

    申请日:2023-09-24

    发明人: Jen-Yuan Chang

    摘要: A method of fabricating a semiconductor package includes: providing a first die group including a plurality of first dies stacked parallel to a front surface of the first die group; providing a second die group including a plurality of second dies parallel to a front surface of the second die group; providing a base substrate structure comprising a substrate characterized by a lattice crystalline plane extending in a third direction; bonding the first die group on the base substrate structure, wherein the first edge extends in a first direction, and the first direction and the third direction define a first angle; and bonding the second die group on the base substrate structure, wherein the second edge extends in a second direction, and the second direction and the third direction define a second angle, and at least one of the first angle and the second angle is not zero.

    PICK-AND-PLACE SYSTEM WITH A STABILIZER
    38.
    发明公开

    公开(公告)号:US20230307281A1

    公开(公告)日:2023-09-28

    申请号:US17700497

    申请日:2022-03-22

    发明人: Jen-Yuan Chang

    摘要: A pick-and-place system is provided. The pick-and-place system includes: a wafer holder configured to hold a bottom die; a gantry having a stabilizer extending downwardly; a primary drive mechanism connected to the gantry and configured to drive the gantry horizontally and vertically; a suction head configured to hold a top die; and a secondary drive mechanism located at the gantry and connected to the suction head and configured to drive the suction head horizontally and vertically to place the top die on the bottom die at a target position. The primary drive mechanism drives the gantry vertically until the stabilizer is in contact with the bottom die before the secondary drive mechanism drives the suction head.

    SEMICONDUCTOR PLACING IN PACKAGING
    39.
    发明申请

    公开(公告)号:US20230137490A1

    公开(公告)日:2023-05-04

    申请号:US17586781

    申请日:2022-01-28

    发明人: Jen-Yuan Chang

    IPC分类号: H01L23/00

    摘要: A method for placing a semiconductor onto a substrate is provided. The method includes the following steps: transferring, using a placement tool, the semiconductor along a path over onto the substrate; lowering, using the placement tool, the semiconductor to a predetermined height above the substrate; titling, using the placement tool, the semiconductor, to a predetermined angle; determining, using the placement tool, a first contact point of the semiconductor to the substrate at the predetermined angle; determining, using the placement tool, the first contact point is shift-off from an alignment position on the semiconductor with respect to the substrate; adjusting, using the placement tool, the first contact point to correct the shift-off; and lowering, using the placement tool, the semiconductor to make a first contact with the substrate at the corrected first contact point.

    MULTI-CHIP PACKAGE HAVING STRESS RELIEF STRUCTURE

    公开(公告)号:US20220352119A1

    公开(公告)日:2022-11-03

    申请号:US17406097

    申请日:2021-08-19

    发明人: Jen-Yuan Chang

    摘要: A semiconductor device includes a package substrate, and a first die group bonded onto the package substrate. The first die group characterized by a first thickness. The semiconductor device also has a second die group bonded onto the package substrate. The second die group characterized by a second thickness. The semiconductor device further includes a carrier substrate disposed on the first die group. The carrier substrate is characterized by a third thickness that is a function of a difference between the first thickness and the second thickness. A molding compound material is disposed on the package substrate and covers the first die group and the second die group. The molding compound material includes a cavity between the first die group and the second die group.