公开(公告)号：US20130087900A1

公开(公告)日：2013-04-11

申请号：US13690386

申请日：2012-11-30

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Juan Alejandro Herbsommer

IPC: H01L23/495

CPC classification number: H01L23/49568 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49562 ,  H01L24/34 ,  H01L2224/32245 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a source region, a gate region and a drain region. A first leadframe subassembly is coupled to the drain region. on a second side of the die are attached to a second leadframe subassembly. A second leadframe subassembly has a first portion electrically coupled with the source region and a second portion electrically coupled with the gate region. The first leadframe subassembly is attached to a third leadframe subassembly. A die is interposed between the first leadframe subassembly and the second leadframe subassembly. The height of the third leadframe subassembly provides a standoff for a distance between the first leadframe subassembly and the second leadframe subassembly.

Abstract translation: 半导体器件包括源极区，栅极区和漏极区。 第一引线框子组件耦合到漏区。 在模具的第二侧上附接到第二引线框子组件。 第二引线框子组件具有与源极区域电耦合的第一部分和与栅极区域电耦合的第二部分。 第一引线框子组件连接到第三引线框子组件。 模具插在第一引线框子组件和第二引线框子组件之间。 第三引线框子组件的高度提供了在第一引线框子组件和第二引线框子组件之间的距离的间隔。

公开(公告)号：US12176274B2

公开(公告)日：2024-12-24

申请号：US16200278

申请日：2018-11-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez ,  Tianyi Luo

IPC: H01L23/495 ,  H01L23/373 ,  H01L23/40 ,  H01L25/065

Abstract: A semiconductor package comprises a first die thermally coupled to a first thermally conductive device. The first thermally conductive device has a first surface exposed to an exterior of the semiconductor package. The package comprises a second die thermally coupled to a second thermally conductive device, the second thermally conductive device having a second surface exposed to an exterior of the semiconductor package. The first and second dies are positioned in different horizontal planes.

公开(公告)号：US11930590B2

公开(公告)日：2024-03-12

申请号：US17218792

申请日：2021-03-31

Applicant: Texas Instruments Incorporated

Inventor： Tianyi Luo ,  Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Bernardo Gallegos

IPC: H05K1/02 ,  H01L21/50 ,  H01L23/00 ,  H01L23/538 ,  H01L21/60

CPC classification number: H05K1/0271 ,  H01L21/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14 ,  H01L2021/60097 ,  H01L2224/16225

Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.

公开(公告)号：US11640932B2

公开(公告)日：2023-05-02

申请号：US17318974

申请日：2021-05-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tianyi Luo ,  Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez

IPC: H01L23/495 ,  H01L25/07 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

公开(公告)号：US20220210911A1

公开(公告)日：2022-06-30

申请号：US17218792

申请日：2021-03-31

Applicant: Texas Instruments Incorporated

Inventor： Tianyi Luo ,  Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Bernardo Gallegos

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/538 ,  H01L21/50

Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.

公开(公告)号：US20220115308A1

公开(公告)日：2022-04-14

申请号：US17518554

申请日：2021-11-03

Applicant: Texas Instruments Incorporated

Inventor： Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Lance Cole Wright ,  Osvaldo Jorge Lopez

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L25/16

Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.

公开(公告)号：US11043477B2

公开(公告)日：2021-06-22

申请号：US16027031

申请日：2018-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez ,  Haian Lin

IPC: H01L23/24 ,  H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H02M3/155 ,  H01L23/48 ,  H01L21/768 ,  H02M3/158

Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.

公开(公告)号：US20210090980A1

公开(公告)日：2021-03-25

申请号：US16581971

申请日：2019-09-25

Applicant: Texas Instruments Incorporated

Inventor： Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Lance Cole Wright ,  Osvaldo Jorge Lopez

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L25/16

Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.

公开(公告)号：US10930582B2

公开(公告)日：2021-02-23

申请号：US15361700

申请日：2016-11-28

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil

IPC: H01L23/495 ,  H01L25/16 ,  H01L25/00 ,  H01L23/00 ,  H01L25/07 ,  H01L23/31 ,  H02M3/155 ,  H01L21/56

Abstract: Disclosed embodiments relate to a semiconductor device. A semiconductor device is fabricated by attachment of a first chip to a first surface of a pad of a leadframe. Each of one or more terminals of the first chip is connected to a respective lead of the leadframe. The first chip and the first surface of the pad are then encapsulated in a packaging material, while leaving an opposite second surface of the pad exposed. A second chip is attached to a recessed portion of the second surface of the pad so that at least one terminal of the second chip is substantially coplanar with an un-recessed portion of the second surface. In one embodiment, a third chip is also attached to the recessed portion of the second surface so that at least one terminal of the third chip is substantially coplanar with the un-recessed portion of the second surface.

公开(公告)号：US20170301596A1

公开(公告)日：2017-10-19

申请号：US15634472

申请日：2017-06-27

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Tom Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L21/48 ,  H01L23/13 ,  H01L23/373 ,  H01L23/00

CPC classification number: H01L23/147 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/3738 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/06181 ,  H01L2224/32225 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/15153 ,  H01L2924/157

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.