公开(公告)号：US10950720B2

公开(公告)日：2021-03-16

申请号：US15790780

申请日：2017-10-23

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  David LaFonteese

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H02H9/04 ,  H01L29/423 ,  H03K19/0185 ,  H01L29/10 ,  H01L29/40

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a p-channel device and an n-channel device. The p-channel device includes an n-type barrier region circumscribing a p-type drain region with an n-type body region. The p-channel device may be positioned adjacent to the n-channel device and a high voltage junction diode.

公开(公告)号：US20200335589A1

公开(公告)日：2020-10-22

申请号：US16918130

申请日：2020-07-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ya ping Chen ,  Hong Yang ,  Peng Li ,  Seetharaman Sridhar ,  Yunlong Liu ,  Rui Liu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

公开(公告)号：US10720499B2

公开(公告)日：2020-07-21

申请号：US16042834

申请日：2018-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ya ping Chen ,  Hong Yang ,  Peng Li ,  Seetharaman Sridhar ,  Yunlong Liu ,  Rui Liu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

公开(公告)号：US10601422B2

公开(公告)日：2020-03-24

申请号：US15809291

申请日：2017-11-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03K17/687 ,  H01L29/06 ,  H03K19/0185 ,  H01L29/78 ,  H01L29/10 ,  H03K17/12 ,  H01L27/092 ,  H01L21/8238

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

公开(公告)号：US10304719B2

公开(公告)日：2019-05-28

申请号：US15413118

申请日：2017-01-23

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Eugen Mindricelu ,  Sameer Pendharkar ,  Seetharaman Sridhar

IPC: H01L27/088 ,  H01L21/761 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/528

Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.

公开(公告)号：US20180097517A1

公开(公告)日：2018-04-05

申请号：US15809291

申请日：2017-11-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03K17/687 ,  H01L27/092 ,  H01L29/06 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/7831 ,  H01L29/7835 ,  H03K17/122

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

公开(公告)号：US09337330B2

公开(公告)日：2016-05-10

申请号：US14572923

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Seetharaman Sridhar

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L29/08 ,  H01L29/10 ,  H01L21/027 ,  H01L21/762 ,  H01L21/266 ,  H01L21/265

CPC classification number: H01L29/7816 ,  H01L21/0271 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor, wherein a diffused drain is deeper under a field oxide element in the drain than in a drift region under the gate. A field oxide hard mask layer is etched to define a drain field oxide trench area. Drain dopants are implanted through the drain field oxide trench area and a thermal drain drive is performed. Subsequently, the drain field oxide element is formed.

Abstract translation: 一种具有扩展漏极MOS晶体管的集成电路和方法，其中扩散漏极在漏极中的场氧化物元件下方比栅极下方的漂移区域更深。 蚀刻场氧化物硬掩模层以限定漏极场氧化物沟槽区域。 通过漏极场氧化物沟槽区域注入漏极掺杂物，并执行热释放驱动。 接着，形成漏极场氧化物元件。

公开(公告)号：US20130105909A1

公开(公告)日：2013-05-02

申请号：US13663015

申请日：2012-10-29

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0883 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

公开(公告)号：US20230395589A1

公开(公告)日：2023-12-07

申请号：US18451292

申请日：2023-08-17

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0259 ,  H01L29/1095 ,  H01L29/7818 ,  H01L29/0878 ,  H01L29/7816 ,  H01L29/0882 ,  H01L29/0619

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US11322594B2

公开(公告)日：2022-05-03

申请号：US17134706

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Fei Ma ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Baoqiang Niu ,  Rui Liu ,  Zhi Peng Feng ,  Seetharaman Sridhar ,  Sunglyong Kim

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/765 ,  H01L29/423 ,  H01L27/24 ,  H01L21/8234

Abstract: A semiconductor device, and methods of forming the same. In one example, the semiconductor device includes a trench in a substrate having a top surface, and a shield within the trench. The semiconductor device also includes a shield liner between a sidewall of the trench and the shield, and a lateral insulator over the shield contacting the shield liner. The semiconductor device also includes a gate dielectric layer on an exposed sidewall of the trench between the lateral insulator and the top surface. The lateral insulator may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer.