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    Memory Compression Operable for Non-contiguous write/read Addresses
    32.
    发明申请
    Memory Compression Operable for Non-contiguous write/read Addresses 审中-公开
    内存压缩可用于非连续写/读地址

    公开(公告)号：US20160110113A1

    公开(公告)日：2016-04-21

    申请号：US14814617

    申请日：2015-07-31

    Applicant: Texas Instruments Incorporated

    Inventor： Sundarrajan Rangachari ,  Desmond Pravin Martin Fernandes ,  Rakesh Channabasappa Yaraduyathinahalli

    IPC: G06F3/06

    CPC classification number: H03M7/30 ,  G06F3/06 ,  G06F13/00 ,  G06F2212/401 ,  H03M7/6047

    Abstract: A digital data storage and retrieval system. The system has a first memory for storing a plurality of data quantities, and each data quantity, in the plurality of data quantities, consists of a first number of bits. The system also has a second memory for storing a plurality of compressed data quantities, and each compressed data quantity, in the plurality of compressed data quantities, consists of a second number of bits that is less than the first number of bits. The system also has circuitry for reading data quantities from the first memory and circuitry for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The system also may include circuitry for reading compressed data quantities from the second memory, and circuitry for writing decompressed data quantities, corresponding to respective read compressed data quantities, to non-sequential addresses in the first memory.

    Abstract translation: 数字数据存储和检索系统。 该系统具有用于存储多个数据量的第一存储器，并且多个数据量中的每个数据量由第一位数组成。 该系统还具有用于存储多个压缩数据量的第二存储器，并且多个压缩数据量中的每个压缩数据量由小于第一位数的第二位数组成。 该系统还具有用于从第一存储器读取数据量的电路和用于将对应于各个读取数据量的压缩数据量写入第二存储器中的非顺序地址的电路。 该系统还可以包括用于从第二存储器读取压缩数据量的电路，以及用于将对应于各个读取的压缩数据量的解压缩数据量写入第一存储器中的非顺序地址的电路。

    LOW-COMPLEXITY INVERSE SINC FOR RF SAMPLING TRANSMITTERS
    34.
    发明申请
    LOW-COMPLEXITY INVERSE SINC FOR RF SAMPLING TRANSMITTERS 有权

    公开(公告)号：US20220029644A1

    公开(公告)日：2022-01-27

    申请号：US17492710

    申请日：2021-10-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jaiganesh Balakrishnan ,  Sriram Murali ,  Sundarrajan Rangachari ,  Yeswanth Guntupalli

    IPC: H04B1/00

    Abstract: A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sin c response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sin c filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.

    Dithered M by N clock dividers
    35.
    发明授权
    Dithered M by N clock dividers 有权

    公开(公告)号：US10651863B1

    公开(公告)日：2020-05-12

    申请号：US16269473

    申请日：2019-02-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sundarrajan Rangachari ,  Sriram Murali ,  Sanjay Pennam

    IPC: H03L7/197 ,  G06F7/58 ,  H03K3/84 ,  H03K21/10 ,  H03K21/02

    Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.

    Multiplier-based programmable filters
    36.
    发明授权
    Multiplier-based programmable filters 有权

    公开(公告)号：US10305451B1

    公开(公告)日：2019-05-28

    申请号：US15839265

    申请日：2017-12-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sundarrajan Rangachari ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu ,  Srinivas Kumar Reddy Naru

    IPC: H03H17/02 ,  H03H17/06

    Abstract: In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.

    Systems and methods of variable fractional rate digital resampling
    39.
    发明授权
    Systems and methods of variable fractional rate digital resampling 有权
    可变分数速率数字重采样的系统和方法

    公开(公告)号：US09531343B2

    公开(公告)日：2016-12-27

    申请号：US14664078

    申请日：2015-03-20

    Applicant: Texas Instruments Incorporated

    Inventor： Jawaharlal Tangudu ,  Sachin Bharadwaj ,  Sundarrajan Rangachari

    IPC: H03K5/00 ,  G06F17/10 ,  H03H11/04

    CPC classification number: H03H11/04 ,  H03H17/0275 ,  H03H17/028 ,  H03H17/0642

    Abstract: Example embodiments of the systems and methods of variable fractional rate digital resampling as disclosed herein achieve variable rate conversion. In the example embodiments, the input samples are upsampled by a factor N in an upsampler followed by a filter which then goes through a linear interpolator. The filter cleans the spectral images of the signal created due to the upsampling operation.

    Abstract translation: 本文公开的可变分数速率数字重采样的系统和方法的示例实施例实现可变速率转换。 在示例实施例中，输入样本在上采样器中由因子N上采样，随后是滤波器，滤波器然后经过线性内插器。 滤波器清除由于上采样操作而产生的信号的光谱图像。

    Systems and methods of low power decimation filter for sigma delta ADC
    40.
    发明授权
    Systems and methods of low power decimation filter for sigma delta ADC 有权
    用于Σ-ΔADC的低功率抽取滤波器的系统和方法

    公开(公告)号：US09391634B1

    公开(公告)日：2016-07-12

    申请号：US14754022

    申请日：2015-06-29

    Applicant: Texas Instruments Incorporated

    Inventor： Sundarrajan Rangachari

    IPC: H03M3/00 ,  H03H17/06 ,  H03M1/12

    CPC classification number: H03M3/462 ,  H03H17/0273 ,  H03H17/06 ,  H03H17/0664 ,  H03H17/0685 ,  H03M1/12 ,  H03M3/30

    Abstract: Example embodiments of the systems and methods of low power decimation filter exploit the single bit data input to the filter and the symmetry of the filter response. The input data may be treated as 0 and 1 instead of −1 and +1. The symmetry of the sinc filter may be exploited since the data across different polyphases are combined. The addition of the symmetric data and coefficient multiplication may be replaced with simple muxing based on two bits and the use of unsigned logic for all adders following coefficient multiplication as both data and coefficient are non-negative.

    Abstract translation: 低功率抽取滤波器的系统和方法的示例实施例利用输入到滤波器的单比特数据和滤波器响应的对称性。 输入数据可以被视为0和1而不是-1和+1。 可以利用sinc滤波器的对称性，因为跨越不同多相的数据被组合。 对称数据和系数乘法的加法可以用基于两个比特的简单复用来代替，并且对于所有加法器使用无符号逻辑，所以在系数乘法之后，数据和系数都是非负的。

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