公开(公告)号：US11594609B2

公开(公告)日：2023-02-28

申请号：US16887577

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chun-I Tsai ,  Chih-Wei Chang ,  Chun-Hsien Huang ,  Hung-Yi Huang ,  Keng-Chu Lin ,  Ken-Yu Chang ,  Sung-Li Wang ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L29/45 ,  H01L23/535 ,  H01L21/768

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

公开(公告)号：US11521929B2

公开(公告)日：2022-12-06

申请号：US17141445

申请日：2021-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chun-I Tsai ,  Chih-Wei Chang ,  Chun-Hsien Huang ,  Hung-Yi Huang ,  Keng-Chu Lin ,  Ken-Yu Chang ,  Sung-Li Wang ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L21/285

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

公开(公告)号：US20210098366A1

公开(公告)日：2021-04-01

申请号：US16844133

申请日：2020-04-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Sung-Li Wang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Fang-Wei Lee

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/285

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

公开(公告)号：US20200273794A1

公开(公告)日：2020-08-27

申请号：US16283838

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A. Khaderbad ,  Keng-Chu Lin ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Yasutoshi Okuno ,  Yu-Yun Peng ,  Chia-Hung Chu

IPC: H01L23/522 ,  H01L29/78 ,  H01L21/768

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate stack and a first dielectric layer over the substrate, a source/drain (S/D) region, a contact, and a via. The first dielectric layer is laterally aside and over the gate stack. The S/D region is located in the substrate on sides of the gate stack. The contact penetrates through the first dielectric layer to electrically connect to the S/D region. The via penetrates through a second dielectric layer to connect to the contact. The via includes a conductive layer and an adhesion promoter layer on sidewalls of the conductive layer. The conductive layer is in contact with the contact.

公开(公告)号：US20240363704A1

公开(公告)日：2024-10-31

申请号：US18771503

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung Chu ,  Tsungyu Hung ,  Hsu-Kai Chang ,  Ding-Kang Shih ,  Keng-Chu Lin ,  Pang-Yen Tsai ,  Sung-Li Wang ,  Shuen-Shin Liang

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.

公开(公告)号：US12080766B2

公开(公告)日：2024-09-03

申请号：US18297854

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung Chu ,  Tsungyu Hung ,  Hsu-Kai Chang ,  Ding-Kang Shih ,  Keng-Chu Lin ,  Pang-Yen Tsai ,  Sung-Li Wang ,  Shuen-Shin Liang

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.

公开(公告)号：US12057397B2

公开(公告)日：2024-08-06

申请号：US18061676

申请日：2022-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chun-I Tsai ,  Chih-Wei Chang ,  Chun-Hsien Huang ,  Hung-Yi Huang ,  Keng-Chu Lin ,  Ken-Yu Chang ,  Sung-Li Wang ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/285 ,  H01L23/522

CPC classification number: H01L23/53266 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/28568 ,  H01L21/76843 ,  H01L23/5226

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

公开(公告)号：US12040372B2

公开(公告)日：2024-07-16

申请号：US17818918

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Kai Chang ,  Jhih-Rong Huang ,  Yen-Tien Tung ,  Chia-Hung Chu ,  Shuen-Shin Liang ,  Tzer-Min Shen ,  Pinyen Lin ,  Sung-Li Wang

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

公开(公告)号：US11929327B2

公开(公告)日：2024-03-12

申请号：US16936335

申请日：2020-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Kai Chang ,  Keng-Chu Lin ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Chia-Hung Chu

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53257 ,  H01L21/76805 ,  H01L21/76883 ,  H01L21/76888 ,  H01L23/5226

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

公开(公告)号：US11810960B2

公开(公告)日：2023-11-07

申请号：US17197892

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li Wang ,  Hsu-Kai Chang ,  Jhih-Rong Huang ,  Yen-Tien Tung ,  Chia-Hung Chu ,  Tzer-Min Shen ,  Pinyen Lin

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/7851

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.