公开(公告)号：US09583399B1

公开(公告)日：2017-02-28

申请号：US15098073

申请日：2016-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Cheng-Hsien Wu ,  Chih Chieh Yeh

IPC: H01L21/306 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/16 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/78618 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/78696

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the first source/drain region. The semiconductor wire in the first source/drain regions is wrapped around by a second semiconductor material.

Abstract translation: 半导体器件包括设置在衬底上的第一沟道层，设置在衬底上的第一源/漏区，设置在每个第一沟道层上并包围第一沟道层的栅极电介质层，以及设置在栅极电介质层上的栅电极层和 缠绕每个第一通道层。 每个第一沟道层包括由第一半导体材料制成的半导体线。 半导体线延伸到第一源/漏区。 第一源极/漏极区域中的半导体线被第二半导体材料缠绕。

公开(公告)号：US09502409B2

公开(公告)日：2016-11-22

申请号：US14624782

申请日：2015-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jon-Hsu Ho ,  Chih-Ching Wang ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Chih Chieh Yeh ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

公开(公告)号：US20230268337A1

公开(公告)日：2023-08-24

申请号：US18305556

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung Wang ,  Chih Chieh Yeh ,  Zi-Ang Su ,  Chia-Ju Chou ,  Ming-Shuan Li

IPC: H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/786

CPC classification number: H01L27/0266 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0296 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78696

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.

公开(公告)号：US11637099B2

公开(公告)日：2023-04-25

申请号：US17224671

申请日：2021-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung Wang ,  Ming-Shuan Li ,  Chih Chieh Yeh ,  Zi-Ang Su ,  Chia-Ju Chou

IPC: H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/786

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a structure having a frontside and a backside, the structure including a substrate and a stack of a first type and a second type epitaxial layers having different material compositions alternatively stacked above the substrate, wherein the stack is at the frontside of the structure and the substrate is at the backside of the structure; patterning the stack, thereby forming a fin above the substrate; implanting a first dopant into a first region of the fin, the first dopant having a first conductivity type; implanting a second dopant into a second region of the fin, the second dopant having a second conductivity type opposite the first conductivity type; and forming a first contact on the first region and a second contact on the second region.

公开(公告)号：US20220302257A1

公开(公告)日：2022-09-22

申请号：US17805719

申请日：2022-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Peng ,  Hung-Li Chiang ,  Yu-Lin Yang ,  Chih Chieh Yeh ,  Yee-Chia Yeo ,  Chi-Wen Liu

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/308 ,  H01L27/12 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423 ,  H01L21/306 ,  H01L21/84

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

公开(公告)号：US11043423B2

公开(公告)日：2021-06-22

申请号：US16595007

申请日：2019-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

公开(公告)号：US20210098305A1

公开(公告)日：2021-04-01

申请号：US16926528

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Chi Yang ,  Allen Chien ,  Cheng-Ting Ding ,  Chien-Chih Lin ,  Chien-Chih Lee ,  Shih-Hao Lin ,  Tsung-Hung Lee ,  Chih Chieh Yeh ,  Po-Kai Hsiao ,  Tsai-Yu Huang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

公开(公告)号：US10516056B2

公开(公告)日：2019-12-24

申请号：US15986426

申请日：2018-05-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Chih Chieh Yeh ,  Cheng-Hsien Wu

IPC: H01L29/786 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/08

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.

公开(公告)号：US10483262B2

公开(公告)日：2019-11-19

申请号：US14714229

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin Yang ,  Chia-Cheng Ho ,  Chih Chieh Yeh ,  Cheng-Yi Peng ,  Tsung-Lin Lee

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165 ,  H01L29/267

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate and forming a first gate structure over a first portion of the fin structure. A first nitride layer is formed over a second portion of the fin structure. The first nitride layer is exposed to ultraviolet radiation. Source/drain regions are formed at the second portion of the fin structure.

公开(公告)号：US20190103472A1

公开(公告)日：2019-04-04

申请号：US15719686

申请日：2017-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  I-Sheng Chen ,  Shao-Ming Yu ,  Tzu-Chiang Chen ,  Chih Chieh Yeh

IPC: H01L29/51 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.