公开(公告)号：US11335552B2

公开(公告)日：2022-05-17

申请号：US16851876

申请日：2020-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Chang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H01L29/66 ,  H01L21/84 ,  H01L21/02 ,  H01L21/768 ,  H01L21/762

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes an oxide semiconductor nanostructure suspended over a substrate. The semiconductor device structure also includes a source/drain structure adjacent to the oxide semiconductor nanostructure. The source/drain structure contains oxygen, and the oxide semiconductor nanostructure has a greater atomic concentration of oxygen than that of the source/drain structure. The semiconductor device structure further includes a gate stack wrapping around the oxide semiconductor nanostructure.

公开(公告)号：US11282945B2

公开(公告)日：2022-03-22

申请号：US16596059

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78

Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.

公开(公告)号：US20220059671A1

公开(公告)日：2022-02-24

申请号：US17521344

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Chih-Yu Chang ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

公开(公告)号：US20210408046A1

公开(公告)日：2021-12-30

申请号：US17125435

申请日：2020-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Chang ,  Meng-Han Lin ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H01L27/11597 ,  H01L27/11587 ,  G11C11/22 ,  H01L29/78

Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

公开(公告)号：US20210375930A1

公开(公告)日：2021-12-02

申请号：US17108218

申请日：2020-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H01L27/11597 ,  H01L29/24 ,  H01L27/1159 ,  H01L21/02 ,  H01L21/425 ,  H01L21/383 ,  H01L21/477

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

公开(公告)号：US20200176585A1

公开(公告)日：2020-06-04

申请号：US16596059

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51

Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.

公开(公告)号：US09711374B2

公开(公告)日：2017-07-18

申请号：US13916827

申请日：2013-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  Chih-Yu Chang ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01L21/321 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/3212 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/32105 ,  H01L29/66545

Abstract: Embodiments of cleaning a surface of a polysilicon layer during a chemical mechanical polishing (CMP) process are provided. The method includes providing a substrate, and forming a gate structure on the substrate, and the gate structure includes a polysilicon layer. The method further includes forming an inter-layer dielectric layer (ILD) over the gate structure. The method also includes performing a CMP process to planarize the inter-layer dielectric layer (ILD) and to expose the polysilicon layer, and the CMP process includes: providing an oxidation solution to a surface of the substrate to perform an oxidation operation to form an oxide layer on the polysilicon layer; and providing a cleaning solution to the surface of the substrate to perform a cleaning operation.

公开(公告)号：US12148843B2

公开(公告)日：2024-11-19

申请号：US18316550

申请日：2023-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yu Chang ,  Hsiang-Pi Chang ,  Zi-Wei Fang

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/324 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device includes a silicon germanium channel, a germanium-free interfacial layer, a high-k dielectric layer, and a metal gate electrode. The silicon germanium channel is over a substrate. The germanium-free interfacial layer is over the silicon germanium channel. The germanium-free interfacial layer is nitridated. The high-k dielectric layer is over the germanium-free interfacial layer. The metal gate electrode is over the high-k dielectric layer.

公开(公告)号：US12136659B2

公开(公告)日：2024-11-05

申请号：US18362064

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Chih-Yu Chang ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/51 ,  H01L21/266 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

公开(公告)号：US12040387B2

公开(公告)日：2024-07-16

申请号：US18358066

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/6684 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.