公开(公告)号：US10658581B2

公开(公告)日：2020-05-19

申请号：US15896134

申请日：2018-02-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hai-Dang Trinh ,  Hsing-Lien Lin ,  Chii-Ming Wu ,  Cheng-Yuan Tsai

IPC: G11C11/56 ,  G11C13/00 ,  H01L45/00

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The semiconductor device structure also includes a first oxide layer over the lower electrode, a second oxide layer over the first oxide layer, and a third oxide layer over the second oxide layer. Oxygen ions are bonded more tightly in the second oxide layer than those in the first oxide layer, and oxygen ions are bonded more tightly in the second oxide layer than those in the third oxide layer. The semiconductor device structure further includes an upper electrode over the third oxide layer.

公开(公告)号：US11482668B2

公开(公告)日：2022-10-25

申请号：US17142591

申请日：2021-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Hsing-Lien Lin ,  Fa-Shen Jiang

IPC: H01L21/336 ,  H01L45/00 ,  H01L27/24 ,  H01L23/528

Abstract: In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device.

公开(公告)号：US11479849B2

公开(公告)日：2022-10-25

申请号：US16429187

申请日：2019-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Shing-Chyang Pan

IPC: C23C14/54 ,  G06N20/00 ,  C23C14/35

Abstract: A sputtering system includes a vacuum chamber, a power source having a pole coupled to a backing plate for holding a sputtering target within the vacuum chamber, a pedestal for holding a substrate within the vacuum chamber, and a time of flight camera positioned to scan a surface of a target held to the backing plate. The time of flight camera may be used to obtain information relating to the topography of the target while the target is at sub-atmospheric pressure. The target information may be used to manage operation of the sputtering system. Managing operation of the sputtering system may include setting an adjustable parameter of a deposition process or deciding when to replace a sputtering target. Machine learning may be used to apply the time of flight camera data in managing the sputtering system operation.

公开(公告)号：US11309491B2

公开(公告)日：2022-04-19

申请号：US16788611

申请日：2020-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Cheng-Yuan Tsai ,  Tzu-Chung Tsai ,  Fa-Shen Jiang

IPC: H01L45/00

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure. A top electrode overlies a bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The second data storage layer is disposed between the first and third data storage layers. The second data storage layer has a lower bandgap than the third data storage layer. The first data storage layer has a lower bandgap than the second data storage layer.

公开(公告)号：US20220084935A1

公开(公告)日：2022-03-17

申请号：US17022320

申请日：2020-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Lien Lin ,  Cheng-Te Lee ,  Rei-Lin Chu ,  Chii-Ming Wu ,  Yeur-Luen Tu ,  Chung-Yi Yu

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/08

Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

公开(公告)号：US20210098398A1

公开(公告)日：2021-04-01

申请号：US16589497

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Julie Yang ,  Chii-Ming Wu ,  Tzu-Chung Tsai ,  Yao-Wen Chang

IPC: H01L23/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die.

公开(公告)号：US20210091169A1

公开(公告)日：2021-03-25

申请号：US16579738

申请日：2019-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Lien Lin ,  Chii-Ming Wu ,  Chia-Shiung Tsai ,  Chung-Yi Yu ,  Rei-Lin Chu

IPC: H01L49/02 ,  H01L23/64 ,  H01L21/02 ,  H01L21/768

Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

公开(公告)号：US20210005487A1

公开(公告)日：2021-01-07

申请号：US16907714

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Tsai ,  Chii-Ming Wu ,  Hai-Dang Trinh

IPC: H01L21/67 ,  G06T7/80 ,  C23C16/455 ,  H04N5/232 ,  C23C14/54 ,  G06T7/00 ,  C23C16/52 ,  C23C14/34

Abstract: In some embodiments, the present disclosure relates to a process tool which includes a housing that defines a vacuum chamber. A wafer chuck is in the housing, and a carrier wafer is on the wafer chuck. A structure that is used for deposition processes is arranged at a top of the housing. A camera is integrated on the wafer chuck such that the camera faces a top of the housing. The camera is configured to wirelessly capture images of the structure used for deposition processes within the housing. Outside of the housing is a wireless receiver. The wireless receiver is configured to receive the images from the camera while the vacuum chamber is sealed.

公开(公告)号：US20200377997A1

公开(公告)日：2020-12-03

申请号：US16429187

申请日：2019-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Shing-Chyang Pan

IPC: C23C14/54 ,  C23C14/35 ,  G06N20/00

Abstract: A sputtering system includes a vacuum chamber, a power source having a pole coupled to a backing plate for holding a sputtering target within the vacuum chamber, a pedestal for holding a substrate within the vacuum chamber, and a time of flight camera positioned to scan a surface of a target held to the backing plate. The time of flight camera may be used to obtain information relating to the topography of the target while the target is at sub-atmospheric pressure. The target information may be used to manage operation of the sputtering system. Managing operation of the sputtering system may include setting an adjustable parameter of a deposition process or deciding when to replace a sputtering target. Machine learning may be used to apply the time of flight camera data in managing the sputtering system operation.

公开(公告)号：US10748798B1

公开(公告)日：2020-08-18

申请号：US16458276

申请日：2019-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Tsai ,  Chii-Ming Wu ,  Hai-Dang Trinh

IPC: H01L21/67 ,  C23C14/54 ,  H04N5/232 ,  C23C16/455 ,  C23C16/52 ,  C23C14/34 ,  G06T7/80 ,  G06T7/00

Abstract: In some embodiments, the present disclosure relates to a process tool which includes a housing that defines a vacuum chamber. A wafer chuck is in the housing and a carrier wafer is on the wafer chuck. A camera is integrated on the wafer chuck such that the camera faces a top of the housing. The camera is configured to wirelessly capture images of an object of interest within the housing. Outside of the housing is a wireless receiver. The wireless receiver is configured to receive the images from the camera while the vacuum chamber is sealed.