公开(公告)号：US20170186691A1

公开(公告)日：2017-06-29

申请号：US15361970

申请日：2016-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Nan Yang ,  Chung-Hsing Wang ,  Yi-Kan Cheng ,  Kumar Lalgudi

IPC: H01L23/528 ,  G06F17/50 ,  H03K5/15

CPC classification number: G06F17/5077 ,  G06F17/5081 ,  G06F2217/62 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H03K5/15066

Abstract: In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line having a first line width and being arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line having a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width can be directly proportional to a first current level for the first clock line and the second line width can be directly proportional to a second current level for the second clock line.

公开(公告)号：US09122839B2

公开(公告)日：2015-09-01

申请号：US14449211

申请日：2014-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Xiang Lee ,  Li-Chung Hsu ,  Shih-Hsien Yang ,  Ho Che Yu ,  King-Ho Tam ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/02 ,  G06F2217/78 ,  G06F2217/84

Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

Abstract translation: 一种方法包括提供一种非暂时的机器可读存储介质，其存储至少部分先前采集的集成电路（IC）布局的部分网表，其表示用于制造具有IC布局的IC的一组光掩模， 该IC满足第一规格值。 计算机识别IC布局中的多个第一设备的正确子集，使得经修订的IC布局中的第二设备对第一设备的正确子集的替换满足与第一规范值不同的第二规范值。 至少一个布局掩模被生成并存储在至少一个非暂时机器可读存储介质中，可由用于形成至少一个附加光掩模的工具访问，使得该组光掩模和至少一个附加光掩模可用于制造 一个IC根据修订的IC布局。

公开(公告)号：US08977991B2

公开(公告)日：2015-03-10

申请号：US14068006

申请日：2013-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Chung-Min Fu ,  Chung-Hsing Wang ,  Wen-Hao Chen ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract translation: 接收到的布局标识要包括在集成电路（IC）层中的多个电路组件，用于使用两个光掩模对层进行双重图案化，所述布局包括要包括在第一光掩模中的多个第一图案和至少一个第二图案 被包括在第二个光掩模中。 所选择的第一模式中的一个具有第一和第二端点，被替换为将第一端点连接到第三端点的替换模式。 除了所选择的第一图案之外，至少一个相应的保留区域被设置为与每个相应的剩余第一图案相邻。 生成表示替换图案的数据，使得在任何保留区域中不形成替换图案的一部分。 输出表示剩余的第一图案和替换图案的数据。

公开(公告)号：US11552068B2

公开(公告)日：2023-01-10

申请号：US17214703

申请日：2021-03-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan Chang ,  Kuo-Nan Yang ,  Chung-Hsing Wang ,  Lee-Chung Lu ,  Sheng-Fong Chen ,  Po-Hsiang Huang ,  Hiranmay Biswas ,  Sheng-Hsiung Chen ,  Aftab Alam Khan

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/118 ,  G06F30/394

Abstract: A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.

公开(公告)号：US11366951B2

公开(公告)日：2022-06-21

申请号：US17204275

申请日：2021-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen Lin ,  Ming-Hsien Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F30/398 ,  G06F30/394 ,  G06F30/367

Abstract: A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.

公开(公告)号：US11282829B2

公开(公告)日：2022-03-22

申请号：US16883740

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Chung-Hsing Wang ,  Yi-Kan Cheng

IPC: H01L27/02 ,  H01L27/092 ,  G06F111/20

Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

公开(公告)号：US11176303B2

公开(公告)日：2021-11-16

申请号：US16686711

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Yuan-Te Hou

IPC: G06F7/50 ,  G06F30/392 ,  G06F111/04

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.

公开(公告)号：US11068637B1

公开(公告)日：2021-07-20

申请号：US16836370

申请日：2020-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chung Hsu ,  Yen-Pin Chen ,  Sung-Yen Yeh ,  Jerry Chang-Jui Kao ,  Chung-Hsing Wang

IPC: G06F30/392 ,  G06F30/367 ,  G06F119/06 ,  G06F113/18

Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

公开(公告)号：US11030381B2

公开(公告)日：2021-06-08

申请号：US16586658

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Hua Liu ,  Yun-Xiang Lin ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F30/398 ,  G06F30/367 ,  G06F30/20 ,  G06F30/39 ,  G06F119/10 ,  G06F30/392 ,  G06F119/18 ,  G06F111/20

Abstract: A method is utilized to calculate a boundary leakage in a semiconductor device. A boundary is detected between a first cell and a second cell, which the first cell and the second cell are abutted to each other around the boundary. Attributes associated with cell edges of the first cell and the second cell are identified. A cell abutment case is identified based on the attributes associated with the cell edges of the first cell and the second cell. An expected boundary leakage between the first cell and the second cell is calculated based on leakage current values associated with the cell abutment case and leakage probabilities associated with the cell abutment case.

公开(公告)号：US10268791B2

公开(公告)日：2019-04-23

申请号：US14967061

申请日：2015-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Chin-Chou Liu ,  Chi-Wei Hu

IPC: G06F17/50

Abstract: A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.