公开(公告)号：US20240280910A1

公开(公告)日：2024-08-22

申请号：US18643281

申请日：2024-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Ming CHANG ,  Chiu-Hsiang CHEN ,  Ru-Gun LIU

IPC: G03F7/00 ,  G03F7/20

CPC classification number: G03F7/70341 ,  G03F7/2004 ,  G03F7/2006 ,  G03F7/2041

Abstract: A method of operating a semiconductor apparatus includes generating an air flow that flows from a covering structure; causing a photomask to move over the covering structure such that particles attached to the photomask are blown away from the photomask by the air flow; and irradiating the photomask with light through a light transmission region of the covering structure.

公开(公告)号：US20210103211A1

公开(公告)日：2021-04-08

申请号：US17121632

申请日：2020-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu An TIEN ,  Hsu-Ting HUANG ,  Ru-Gun LIU

IPC: G03F1/36 ,  G03F1/70

Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.

公开(公告)号：US20210096473A1

公开(公告)日：2021-04-01

申请号：US16587710

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Huicheng CHANG ,  Chia-Cheng CHEN ,  Jyu-Horng SHIEH ,  Liang-Yin CHEN ,  Shu-Huei SUEN ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yi-Nien SU ,  Yung-Sung YEN ,  Chia-Fong CHANG ,  Ya-Wen YEH ,  Yu-Tien SHEN

IPC: G03F7/20 ,  H01L21/027

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

公开(公告)号：US20210066091A1

公开(公告)日：2021-03-04

申请号：US16894545

申请日：2020-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Min HSIAO ,  Chien-Wen LAI ,  Ru-Gun LIU ,  Chih-Ming LAI ,  Wei-Shuo SU ,  Yu-Chen CHANG

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

Abstract: A four signal line unit cell is formed on a substrate using a combination of an extreme ultraviolet photolithography process and one or more self aligned deposition processes. The photolithography process and the self aligned deposition processes result in spacers on a hard mask above the substrate. The spacers define a pattern of signal lines to be formed on the substrate for a unit cell. The photolithography process and self aligned deposition processes result in signal lines having a critical dimension much smaller than features that can be defined by the extreme ultraviolet photolithography process.

公开(公告)号：US20200096857A1

公开(公告)日：2020-03-26

申请号：US16554318

申请日：2019-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Ting HUANG ,  Ru-Gun LIU

IPC: G03F1/36 ,  G03F1/70 ,  G06F17/50

Abstract: Provided is a method for fabricating a semiconductor device including performing an OPC process to an IC layout pattern to generate a post-OPC layout pattern. In some embodiments, the method further includes applying an MPC model to the post-OPC layout pattern to generate a simulated mask pattern. By way of example, the simulated mask pattern is compared to a mask pattern calculated from a target wafer pattern. Thereafter, and based on the comparing, an outcome of an MPC process is determined.

公开(公告)号：US20200066523A1

公开(公告)日：2020-02-27

申请号：US16669065

申请日：2019-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming LAI ,  Shih-Ming CHANG ,  Wei-Liang LIN ,  Chin-Yuan TSENG ,  Ru-Gun LIU

IPC: H01L21/033 ,  H01L21/311

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure.

公开(公告)号：US20200006078A1

公开(公告)日：2020-01-02

申请号：US16240402

申请日：2019-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Chih-Ming LAI ,  Wei-Liang LIN ,  Yung-Sung YEN ,  Ken-Hsien HSIEH ,  Chin-Hsiang LIN

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

公开(公告)号：US20200004137A1

公开(公告)日：2020-01-02

申请号：US16287450

申请日：2019-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Chin-Hsiang LIN ,  Cheng-I HUANG ,  Chih-Ming LAI ,  Lai Chien WEN ,  Ken-Hsien HSIEH ,  Shih-Ming CHANG ,  Yuan-Te HOU

IPC: G03F1/42 ,  G03F1/50 ,  G03F1/68 ,  G03F7/20

Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.

公开(公告)号：US20190146333A1

公开(公告)日：2019-05-16

申请号：US15966962

申请日：2018-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ken-Hsien HSIEH ,  Ru-Gun LIU ,  Wei-Shuo SU

IPC: G03F1/70 ,  H01L21/311 ,  G03F1/36

Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

公开(公告)号：US20190096909A1

公开(公告)日：2019-03-28

申请号：US16022821

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Cheng-Chi CHUANG ,  Chih-Ming LAI ,  Chia-Tien WU ,  Charles Chew-Yuen YOUNG ,  Hui-Ting YANG ,  Jiann-Tyng TZENG ,  Ru-Gun LIU ,  Wei-Cheng LIN ,  Lei-Chun CHOU ,  Wei-An LAI

IPC: H01L27/118 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.