公开(公告)号：US20190088650A1

公开(公告)日：2019-03-21

申请号：US16195258

申请日：2018-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Chun-Liang Lai ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/027

Abstract: A method includes providing a structure having a substrate, semiconductor fins, and an isolation structure between adjacent semiconductor fins; forming a first gate structure engaging the semiconductor fins; depositing an inter-layer dielectric layer over the semiconductor fins and the first gate structure; removing the first gate structure, resulting in a first trench; depositing a second gate structure into the first trench, wherein the second gate structure includes a dielectric layer and a conductive layer; forming one or more mask layers over the second gate structure; patterning the one or more mask layers to have an opening exposing a portion of the second gate structure between two adjacent semiconductor fins; and etching the second gate structure through the opening to produce a second trench having tapered sidewalls, wherein the second trench is wider at top than at bottom.

公开(公告)号：US20190067277A1

公开(公告)日：2019-02-28

申请号：US15904835

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Chun-Liang Lai ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, first and second fins protruding out of the substrate, and first and second high-k metal gates (HK MG) disposed over the first and second fins, respectively. From a top view, the first and second fins are arranged lengthwise along a first direction, the first and second HK MG are arranged lengthwise along a second direction generally perpendicular to the first direction, and the first and second HK MG are aligned along the second direction. In a cross-sectional view cut along the second direction, the first HK MG has a first sidewall that is slanted from top to bottom towards the second HK MG, and the second HK MG has a second sidewall that is slanted from top to bottom towards the first HK MG. Methods for producing the semiconductor device are also disclosed.

公开(公告)号：US20240371869A1

公开(公告)日：2024-11-07

申请号：US18775025

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ryan Chia-Jen Chen ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yu-Hsien Lin ,  Ming-Ching Chang ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Yi-Chun Chen

IPC: H01L27/088 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

公开(公告)号：US11915980B2

公开(公告)日：2024-02-27

申请号：US18064726

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Yi-Hsuan Hsiao ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823437 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

公开(公告)号：US20230377990A1

公开(公告)日：2023-11-23

申请号：US18365420

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Li-Wei Yin ,  Chen-Huang Huang ,  Ming-Jhe Sie ,  Ryan Chia-Jen Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0924 ,  H01L21/3065 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/76829 ,  H01L29/66545

Abstract: In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.

公开(公告)号：US11823958B2

公开(公告)日：2023-11-21

申请号：US17379469

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Li-Wei Yin ,  Chen-Huang Huang ,  Ming-Jhe Sie ,  Ryan Chia-Jen Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L21/823821 ,  H01L21/3065 ,  H01L21/76829 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.

公开(公告)号：US11810909B2

公开(公告)日：2023-11-07

申请号：US17218284

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku ,  Ming-Ching Chang

IPC: H01L27/02 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/762 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/06 ,  H01L21/027 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L27/0207 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L21/0276 ,  H01L21/28556 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636

Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.

公开(公告)号：US11721588B2

公开(公告)日：2023-08-08

申请号：US17341163

申请日：2021-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chang Hung ,  Shu-Yuan Ku ,  I-Wei Yang ,  Yi-Hsuan Hsiao ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823481

Abstract: The first and second fins extend upwardly from a semiconductor substrate. The shallow trench isolation structure laterally surrounds lower portions of the first and second fins. The first gate structure extends across an upper portion of the first fin. The second gate structure extends across an upper portion of the second fin. The first source/drain epitaxial structures are on the first fin and on opposite sides of the first gate structure. The second source/drain epitaxial structures are on the second fin and on opposite sides of the second gate structure. The separation plug interposes the first and second gate structures and extends along a lengthwise direction of the first fin. The isolation material cups an underside of a portion of the separation plug between one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures.

公开(公告)号：US11616061B2

公开(公告)日：2023-03-28

申请号：US16195258

申请日：2018-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Chun-Liang Lai ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/311 ,  H01L21/027 ,  H01L21/3105

Abstract: A method includes providing a structure having a substrate, semiconductor fins, and an isolation structure between adjacent semiconductor fins; forming a first gate structure engaging the semiconductor fins; depositing an inter-layer dielectric layer over the semiconductor fins and the first gate structure; removing the first gate structure, resulting in a first trench; depositing a second gate structure into the first trench, wherein the second gate structure includes a dielectric layer and a conductive layer; forming one or more mask layers over the second gate structure; patterning the one or more mask layers to have an opening exposing a portion of the second gate structure between two adjacent semiconductor fins; and etching the second gate structure through the opening to produce a second trench having tapered sidewalls, wherein the second trench is wider at top than at bottom.

公开(公告)号：US20220384271A1

公开(公告)日：2022-12-01

申请号：US17883898

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chieh-Ning Feng ,  Chun-Liang Lai ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/08

Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.