公开(公告)号：US20200066581A1

公开(公告)日：2020-02-27

申请号：US16672879

申请日：2019-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Yu-Kai Lin ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/311

Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.

公开(公告)号：US20190006227A1

公开(公告)日：2019-01-03

申请号：US15725996

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Lin TSAI ,  Shing-Chyang Pan ,  Sung-En Lin ,  Tze-Liang Lee ,  Jung-Hau Shiu ,  Jen Hung Wang

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02019 ,  H01L21/0337 ,  H01L2221/101

Abstract: The present disclosure describes a method of forming a dielectric layer or a dielectric stack on a photoresist layer while minimizing or avoiding damage to the photoresist. In addition, the dielectric layer or dielectric stack can till high-aspect ratio openings and can be removed with etching. The dielectric layer or dielectric stack can be deposited with a conformal, low-temperature chemical vapor deposition process or a conformal, low-temperature atomic layer deposition process that utilizes a number of precursors and plasmas or reactant gases.

公开(公告)号：US20180005876A1

公开(公告)日：2018-01-04

申请号：US15197294

申请日：2016-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

公开(公告)号：US11991930B2

公开(公告)日：2024-05-21

申请号：US17984066

申请日：2022-11-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/80

Abstract: A structure includes a substrate, a transistor, a contact, an oxygen-free etch stop layer, an oxygen-containing etch stop layer, a dielectric layer, and a via. The transistor is on the substrate. The contact is on a source/drain region of the transistor. The oxygen-free etch stop layer spans the contact. The oxygen-containing etch stop layer extends along a top surface of the oxygen-free etch stop layer. The dielectric layer is over the oxygen-containing etch stop layer. The via passes through the dielectric layer, the oxygen-containing etch stop layer, and the oxygen-free etch stop layer and lands on the contact. The memory stack lands on the via.

公开(公告)号：US11651993B2

公开(公告)日：2023-05-16

申请号：US16876965

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/485

CPC classification number: H01L21/76829 ,  H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53238 ,  H01L23/53295 ,  H01L21/76807 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53266

Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

公开(公告)号：US11322396B2

公开(公告)日：2022-05-03

申请号：US16043343

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/485

Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

公开(公告)号：US20210280780A1

公开(公告)日：2021-09-09

申请号：US16807600

申请日：2020-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Zhong ,  Cheng-Yuan Tsai ,  Hai-Dang Trinh ,  Shing-Chyang Pan

IPC: H01L45/00 ,  H01L27/24

Abstract: Some embodiments relate to a memory device. The memory device includes a bottom electrode overlying a substrate. A data storage layer overlies the bottom electrode. A top electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the bottom electrode to the top electrode. A diffusion barrier layer is disposed between the data storage layer and the top electrode.

公开(公告)号：US10862026B2

公开(公告)日：2020-12-08

申请号：US16741557

申请日：2020-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, a metal nitride layer, an etch stop layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The metal nitride layer spans the first dielectric layer and the metal contact. The etch stop layer extends along a top surface of the metal nitride layer, in which a thickness of the metal nitride layer is less than a thickness of the etch stop layer. The second dielectric layer is over the etch stop layer. The metal via passes through the second dielectric layer, the etch stop layer, and the metal nitride layer and lands on the metal contact. The memory stack is in contact with the metal via.

公开(公告)号：US09818638B1

公开(公告)日：2017-11-14

申请号：US15490233

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Yun Peng ,  Chung-Chi Ko ,  Shing-Chyang Pan

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/53295

Abstract: A method of forming a semiconductor device includes forming a low-k dielectric layer over a substrate and forming a first dielectric layer on the low-k dielectric layer. A first metal hard mask layer is formed on the first dielectric layer, and a second dielectric layer is formed on the first metal hard mask layer. A second metal hard mask layer is formed on the second dielectric layer, and a first trench opening is formed in the second metal hard mask layer and the second dielectric layer exposing the first metal hard mask layer. A first via opening is formed in the exposed first metal hard mask layer in the first trench opening, and the first trench opening and first via opening are extended into the low-k dielectric layer to form a first trench and a first via.

公开(公告)号：US09659811B1

公开(公告)日：2017-05-23

申请号：US15204801

申请日：2016-07-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Yun Peng ,  Chung-Chi Ko ,  Shing-Chyang Pan

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/53295

Abstract: A method of forming a semiconductor device includes forming a low-k dielectric layer over a substrate and forming a first dielectric layer on the low-k dielectric layer. A first metal hard mask layer is formed on the first dielectric layer, and a second dielectric layer is formed on the first metal hard mask layer. A second metal hard mask layer is formed on the second dielectric layer, and a first trench opening is formed in the second metal hard mask layer and the second dielectric layer exposing the first metal hard mask layer. A first via opening is formed in the exposed first metal hard mask layer in the first trench opening, and the first trench opening and first via opening are extended into the low-k dielectric layer to form a first trench and a first via.