公开(公告)号：US20220270934A1

公开(公告)日：2022-08-25

申请号：US17662569

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting PAN ,  Huan-Chieh SU ,  Zhi-Chang LIN ,  Shi Ning JU ,  Yi-Ruei JHAN ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

公开(公告)号：US20200243666A1

公开(公告)日：2020-07-30

申请号：US16683512

申请日：2019-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Zhi-Chang LIN ,  Kuan-Ting PAN ,  Chih-Hao WANG ,  Shi-Ning JU

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L21/033 ,  H01L21/8234

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked wire structure and a second stacked wire structure extending above the isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first stacked wire structure and the second stacked wire structure. The semiconductor device structure also includes a capping layer formed over the dummy fin structure. The isolation structure has a first width, the dummy fin structure has a second width, and the second width is smaller than the first width.

公开(公告)号：US20200098888A1

公开(公告)日：2020-03-26

申请号：US16142672

申请日：2018-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang LIN ,  Wei-Hao WU ,  Jia-Ni YU

IPC: H01L29/66 ,  H01L23/535 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.

公开(公告)号：US20200035558A1

公开(公告)日：2020-01-30

申请号：US16422559

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Lin-Yu HUANG ,  Huan-Chieh SU ,  Sheng-Tsung WANG ,  Zhi-Chang LIN ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/40 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.

公开(公告)号：US20240395859A1

公开(公告)日：2024-11-28

申请号：US18789465

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang LIN ,  Chien Ning YAO ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Tsung-Han CHUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/786

Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.

公开(公告)号：US20240355908A1

公开(公告)日：2024-10-24

申请号：US18759649

申请日：2024-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Han CHUANG ,  Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Chien Ning YAO ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.

公开(公告)号：US20240332073A1

公开(公告)日：2024-10-03

申请号：US18738390

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang LIN ,  Wei-Hao WU ,  Teng-Chun TSAI

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L21/76835 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53295 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4232

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.

公开(公告)号：US20230369469A1

公开(公告)日：2023-11-16

申请号：US18357464

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Cheng CHEN ,  Kuo-Cheng CHIANG ,  Zhi-Chang LIN

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785

Abstract: A method of fabricating a device includes providing a fin having a plurality of channel layers and a plurality of multilayer epitaxial layers interposing the plurality of channel layers. The multilayer epitaxial layers include a first epitaxial layer interposed between second and third epitaxial layers. The first epitaxial layer has a first etch rate and the second and third epitaxial layers have a second etch rate greater than the first etch rate. The method further includes laterally etching the first, second, and third epitaxial layers to provide a convex sidewall profile on opposing lateral surfaces of the multilayer epitaxial layers. The method further includes forming an inner spacer between adjacent channel layers. The inner spacer interfaces the convex sidewall profile of the multilayer epitaxial layers along a first inner spacer sidewall surface. The method further includes replacing the multilayer epitaxial layers with a portion of a gate structure.

公开(公告)号：US20230028900A1

公开(公告)日：2023-01-26

申请号：US17693204

申请日：2022-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang LIN ,  Chien Ning YAO ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Tsung-Han CHUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.

公开(公告)号：US20220416036A1

公开(公告)日：2022-12-29

申请号：US17576748

申请日：2022-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Cheng CHEN ,  Zhi-Chang LIN ,  Jung-Hung CHANG ,  Chien-Ning YAO ,  Tsung-Han CHUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.