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    Data processor having unified memory architecture providing priority memory access
    33.
    发明授权
    Data processor having unified memory architecture providing priority memory access 失效
    数据处理器具有统一的存储器架构，提供优先存储器

    公开(公告)号：US06717583B2

    公开(公告)日：2004-04-06

    申请号：US09991705

    申请日：2001-11-26

    申请人： Tetsuya Shimomura ,  Shigeru Matsuo ,  Koyo Katsura ,  Tatsuki Inuzuka ,  Yasuhiro Nakatsuka

    发明人： Tetsuya Shimomura ,  Shigeru Matsuo ,  Koyo Katsura ,  Tatsuki Inuzuka ,  Yasuhiro Nakatsuka

    IPC分类号： G06F15167

    CPC分类号： G09G5/001 ,  G06F13/1673 ,  G06F13/18 ,  G09G5/02 ,  G09G5/363 ,  G09G5/393 ,  G09G5/395 ,  G09G2340/02 ,  G09G2360/121 ,  G09G2360/125 ,  G09G2360/128

    摘要： In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.

    摘要翻译： 为了减少由于使用主存储器的一部分作为显示帧缓冲器而导致的数据处理器的处理性能的劣化，当从CPU 310产生对存储器200的访问请求时，存储器控制器400保持 一旦请求显示控制器560停止对正在执行的存储器200的访问，当已经从存储器200传送已经执行的访问的数据时，显示控制器560保持它，并且从被保持的CPU总线310传送访问请求 当CPU总线310的访问结束时，存储器控制器400重新启动在显示控制器560中停止的访问，并将保持的数据传送到显示控制器560。

    Information providing system
    35.
    发明授权
    Information providing system 失效
    信息提供系统

    公开(公告)号：US06324467B1

    公开(公告)日：2001-11-27

    申请号：US09518908

    申请日：2000-03-03

    申请人： Kimiyoshi Machii ,  Kazuyoshi Koga ,  Shigeru Matsuo ,  Yoshitaka Atarashi ,  Soshiro Kuzunuki ,  Keiko Abe ,  Toshimi Yokota

    发明人： Kimiyoshi Machii ,  Kazuyoshi Koga ,  Shigeru Matsuo ,  Yoshitaka Atarashi ,  Soshiro Kuzunuki ,  Keiko Abe ,  Toshimi Yokota

    IPC分类号： G01C2100

    CPC分类号： G08G1/096811 ,  G01C21/32 ,  G01C21/3655 ,  G08G1/096816 ,  G08G1/096822 ,  G08G1/096838 ,  G08G1/096861 ,  G08G1/096894

    摘要： An information providing system is capable of rendering map-information services even if the size of a free area in a memory employed in a terminal becomes small, disallowing all details of a map to be downloaded. A server employed in the information providing system has a search engine for searching a map data base for a map suitable for a destination and the present position of the terminal as received from the terminal, a route computing unit for computing a guide route from the present position to the destination, a map display location determination unit for determining a location at which route information including a map based on the calculated guide route is to be transmitted to the terminal and a thinning determination unit for thinning the information to be transmitted based on information on the terminal received from the terminal. The thinning determination unit has a priority-level definition table for defining priority levels assigned to map elements stored in the map data base.

    摘要翻译： 即使终端中使用的存储器中的空闲区域的大小变小，信息提供系统也能够呈现地图信息服务，不允许下载地图的所有细节。 在信息提供系统中使用的服务器具有搜索引擎，用于在从地图数据库中搜索适合于目的地的地图和从终端接收到的终端的当前位置;路线计算单元，用于从当前计算引导路线 位置到目的地，地图显示位置确定单元，用于基于所计算的引导路线将包括地图的路线信息的位置确定到终端;以及间隔确定单元，用于基于信息来稀疏要发送的信息 在从终端接收的终端上。 稀疏确定单元具有用于定义分配给存储在地图数据库中的地图元素的优先级的优先级级别定义表。

    Data processor for processing a complex instruction by dividing it into executing units
    36.
    发明授权
    Data processor for processing a complex instruction by dividing it into executing units 失效
    数据处理器，用于通过将复杂指令分为执行单元来处理

    公开(公告)号：US6092183A

    公开(公告)日：2000-07-18

    申请号：US401691

    申请日：1995-03-10

    申请人： Hidehito Takewa ,  Shigeru Matsuo ,  Shinji Fujiwara ,  Masahisa Narita

    发明人： Hidehito Takewa ,  Shigeru Matsuo ,  Shinji Fujiwara ,  Masahisa Narita

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3802 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3861 ,  G06F9/3867

    摘要： A compact and small compensating-electric-power data processor is realized by dividing a plurality of calculations to be carried out by a complex instruction into a number of executing units to be processed, instead of executing the calculations in parallel as in the past. For this purpose there is provided a decoder having a detecting part for decoding an instruction and for detecting whether the instruction is an instruction for executing a plurality of calculations, a field rearranging part for rearranging a part of the fields of said instruction based on a predetermined number of calculations to be processed if it is judged by said detecting part that the instruction is an instruction for executing a plurality of calculations, and a calculation control part for performing control to execute the calculations in plural cycles in synchronism with the order of said rearranged fields. A calculation part operates to execute the calculations called for by dividing the instruction into plural cycles based on control from the calculation control part.

    摘要翻译： 通过将要由复杂指令执行的多个计算划分成要处理的多个执行单元来实现紧凑而小的补偿电力数据处理器，而不是如以前那样并行地执行计算。 为此，提供了一种解码器，具有用于对指令进行解码并检测该指令是否是用于执行多个计算的指令的检测部分，用于基于预定的方式重排所述指令的一部分字段的字段重排部分 如果由所述检测部分判断所述指令是用于执行多个计算的指令，则要处理的计算次数以及用于执行控制以与所述重新排列的顺序同步地执行多个周期的计算的计算控制部分 领域。 计算部分通过根据来自计算控制部分的控制将指令分成多个周期来进行所需的计算。

    Graphic processor suitable for graphic data transfer and conversion processes
    38.
    发明授权
    Graphic processor suitable for graphic data transfer and conversion processes 失效
    图形处理器适用于图形数据传输和转换过程

    公开(公告)号：US5202962A

    公开(公告)日：1993-04-13

    申请号：US544503

    申请日：1990-06-27

    申请人： Shigeru Matsuo ,  Koyo Katsura ,  Jun Sato ,  Takashi Sone ,  Masakatu Yokoyama

    发明人： Shigeru Matsuo ,  Koyo Katsura ,  Jun Sato ,  Takashi Sone ,  Masakatu Yokoyama

    IPC分类号： G06T17/00

    CPC分类号： G06T17/00

    摘要： A graphic processor which controls reading, writing and transfer of graphic data for a display memory that stores graphic data. The processor includes a first unit which stores first address information for addressing the display memory and first pixel address information which points a pixel position in a word specified by the first address information, a second unit which stores second address information for addressing the display memory and second pixel address information which points a pixel position in a word specified by the second address information, a third unit which shifts graphic data of multiple pixels included in two consecutive words to extract continuous 1-word graphic data, and a fourth unit which implements drawing computations pixel-wise concurrently for one word depending on the number of pixels included in a word. Even if transfer source graphic data lies across two consecutive words, the processor fetches the source data in single reading, processes the data word-wise at once, and stores the result in the display memory.

    摘要翻译： 用于控制用于存储图形数据的显示存储器的图形数据的读取，写入和传送的图形处理器。 处理器包括第一单元，其存储用于寻址显示存储器的第一地址信息和指向由第一地址信息指定的字中的像素位置的第一像素地址信息;第二单元，存储用于寻址显示存储器的第二地址信息;以及 指定由第二地址信息指定的字中的像素位置的第二像素地址信息;移动包括在两个连续字中的多个像素的图形数据以提取连续的1字图形数据的第三单元;以及实现绘图的第四单元 根据包含在一个单词中的像素数量，对一个单词进行像素同步的计算。 即使传输源图形数据位于两个连续的字中，处理器以单次读取的方式读取源数据，一次处理数据，并将结果存储在显示存储器中。

    Cursor display control method and apparatus in a graphic display system
    39.
    发明授权
    Cursor display control method and apparatus in a graphic display system 失效
    图形显示系统中的光标显示控制方法和装置

    公开(公告)号：US5192943A

    公开(公告)日：1993-03-09

    申请号：US583584

    申请日：1990-09-17

    申请人： Shigeru Matsuo ,  Tadashi Fukushima ,  Tooru Komagawa ,  Masahisa Narita

    发明人： Shigeru Matsuo ,  Tadashi Fukushima ,  Tooru Komagawa ,  Masahisa Narita

    IPC分类号： G06F3/14 ,  G06F3/048 ,  G09G5/08

    CPC分类号： G09G5/08

    摘要： A cursor display control in a graphic display system is provided in which a storage range is provided for exclusive use for a cursor pattern and a desired shape is defined in the storage range to thereby perform a high-speed cursor movement. A display control apparatus in the graphic display system includes a memory for storing a cursor pattern, shift register for performing a shift processing in a non-display period of the cursor for positioning in the display screen, and parallel-serial converter for performing parallel to serial conversion at the display timing of the cursor, whereby the apparatus is suitable to be integrated in the form of an LSI and the cursor can be moved at a high speed on the screen.

    Font data processor using addresses calculated on the basis of access parameters
    40.
    发明授权
    Font data processor using addresses calculated on the basis of access parameters 失效
    使用基于访问参数计算的地址的FONT数据处理器

    公开(公告)号：US5175811A

    公开(公告)日：1992-12-29

    申请号：US804462

    申请日：1991-12-05

    申请人： Takashi Sone ,  Jun Sato ,  Koyo Katsura ,  Shigeru Matsuo

    发明人： Takashi Sone ,  Jun Sato ,  Koyo Katsura ,  Shigeru Matsuo

    IPC分类号： G09G5/24 ,  G06F3/14 ,  G06F15/62 ,  G09G5/22

    CPC分类号： G09G5/24

    摘要： A font processing system includes font pattern storage for defining a font pattern and font pattern access parameter storage for storing parameters for making access to the font pattern storage. Address calculation is made on the basis of the font pattern access parameter and a pattern code supplied from outside to indicate a font pattern. The font pattern processing system includes a pattern drawing attribute indicator for indicating the attributes of pattern drawing by the font pattern data thus read out. The present invention processes predetermined font data at a high speed inside a font data processor on the basis of the pattern code and can easily accomplish diversification of font patterns.

    摘要翻译： 字体处理系统包括用于定义字体图案的字体图案存储和用于存储用于访问字体图案存储的参数的字体图案访问参数存储。 基于字体图案访问参数和从外部提供的图案代码来指示字体图案进行地址计算。 字体图案处理系统包括用于通过读出的字体图案数据指示图案绘制的属性的图案绘图属性指示符。 本发明基于图案代码在字体数据处理器内高速处理预定的字体数据，并且可以容易地实现字体图案的多样化。