公开(公告)号：US06867100B2

公开(公告)日：2005-03-15

申请号：US10326214

申请日：2002-12-19

申请人： Henry L. Edwards ,  Sameer Pendharkar ,  Joe Trogolo ,  Tathagata Chatterjee ,  Taylor Efland

发明人： Henry L. Edwards ,  Sameer Pendharkar ,  Joe Trogolo ,  Tathagata Chatterjee ,  Taylor Efland

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7801

摘要： The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.

摘要翻译： 本发明提供了一种用于有效地生产多功能，高精度的MOS器件结构的系统，其中直线区域主导器件的行为，以简单，高效和成本有效的方式提供精确匹配大型器件的最小几何器件。 本发明提供了用于生产双扩散半导体器件的方法和装置，其最小化端帽区域的性能影响。 本发明提供一种MOS结构，其具有护城河区域（404,516,616）和与护城河区域重叠的氧化物区域（414,512,608）。 在氧化物区域内形成双扩散区域（402,504,618），具有端盖区域（406,502,620），其可以利用几何和植入操作被有效地去激活。

公开(公告)号：US08890248B2

公开(公告)日：2014-11-18

申请号：US10926916

申请日：2004-08-26

申请人： Timothy Patrick Pauletti ,  Sameer Pendharkar ,  Wayne Tien-Feng Chen ,  Jonathan Brodsky ,  Robert Steinhoff

发明人： Timothy Patrick Pauletti ,  Sameer Pendharkar ,  Wayne Tien-Feng Chen ,  Jonathan Brodsky ,  Robert Steinhoff

IPC分类号： H01L23/62 ,  H01L29/74 ,  H01L27/02 ,  H01L29/87 ,  H01L29/749

CPC分类号： H01L27/0262 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.

摘要翻译： 一种用于保护电路的输入/输出端子的静电放电（ESD）装置，该装置包括：第一晶体管，其具有耦合在电路的输入/输出（I / O）端子之间的集成硅控整流器（SCR） 节点和第二晶体管，其具有耦合在所述节点和电源电压的负端子之间的集成硅控整流器，其中所述第一晶体管的所述硅控整流器响应于ESD ESD电压而触发，并且所述可硅可控整流器 的第二晶体管响应于正的ESD电压而触发。

公开(公告)号：US08878284B2

公开(公告)日：2014-11-04

申请号：US13460523

申请日：2012-04-30

申请人： Sameer Pendharkar ,  Suhail Murtaza ,  Juergen Wittmann

发明人： Sameer Pendharkar ,  Suhail Murtaza ,  Juergen Wittmann

IPC分类号： H01L29/66

CPC分类号： H01L29/0692 ,  H01L29/87

摘要： A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type (314) formed within and electrically connected to a first lightly doped region of the second conductivity type (310, 312). A cathode circuit having a plurality of third heavily doped regions of the first conductivity type (700) within a second heavily doped region of the second conductivity type (304). A first lead (202) is connected to each third heavily doped region (704) and connected to the second heavily doped region by at least three spaced apart connections (702) between every two third heavily doped regions. An SCR (400, 402) is connected between the anode circuit and the cathode circuit. The DMOS transistor has a drain (310, 312, 316) connected to the anode circuit and a source (304) connected to the cathode circuit.

摘要翻译： 用于DMOS晶体管的保护电路包括阳极电路，其具有在第二导电类型（310,312）的第一轻掺杂区域内形成并电连接的第一导电类型的第一重掺杂区域（314）。 在第二导电类型（304）的第二重掺杂区域内具有第一导电类型（700）的多个第三重掺杂区域的阴极电路。 第一引线（202）连接到每个第三重掺杂区域（704），并且通过每两个第三重掺杂区域之间的至少三个间隔开的连接（702）连接到第二重掺杂区域。 在阳极电路和阴极电路之间连接有SCR（400,402）。 DMOS晶体管具有连接到阳极电路的漏极（310,312,316）和连接到阴极电路的源极（304）。

公开(公告)号：US20140001596A1

公开(公告)日：2014-01-02

申请号：US13540542

申请日：2012-07-02

申请人： Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur ,  Tamura Takehito

发明人： Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur ,  Tamura Takehito

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/02109 ,  H01L21/265 ,  H01L21/283 ,  H01L21/32055 ,  H01L21/76232 ,  H01L29/0619

摘要： The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.

摘要翻译： 通过形成重掺杂沉降片位于已形成于半导体材料中的多个紧密间隔的沟槽隔离结构之间，大大减小了重掺杂沉降片的宽度。 在进入期间，紧密间隔的沟槽隔离结构显着限制了横向扩散。

公开(公告)号：US08580650B2

公开(公告)日：2013-11-12

申请号：US13284054

申请日：2011-10-28

申请人： Marie Denison ,  Sameer Pendharkar

发明人： Marie Denison ,  Sameer Pendharkar

IPC分类号： H01L21/76

CPC分类号： H01L29/7816 ,  H01L21/76224 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.

摘要翻译： 一种集成电路，其包含在漂移区域中具有深半导体（SC）RESURF沟槽的扩展漏极MOS晶体管，其中每个深的SC RESURF沟槽在与漂移区接触的沟槽的侧壁处具有半导体RESURF层。 半导体RESURF层具有与漂移区相反的导电类型。 深的SC RESURF沟槽具有至少5：1的深度：宽度比，并且不延伸穿过漂移区域的底部表面。 通过蚀刻尺寸不足的沟槽和反向掺杂侧壁区以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。 通过蚀刻沟槽并在侧壁区域上生长外延层以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。

公开(公告)号：US08470675B2

公开(公告)日：2013-06-25

申请号：US13274698

申请日：2011-10-17

申请人： Seetharaman Sridhar ,  Sameer Pendharkar

发明人： Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L21/8234

CPC分类号： H01L21/823456 ,  H01L21/823462

摘要： A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor.

摘要翻译： 一种形成集成电路的工艺，包括形成用于离子注入低电压晶体管的虚拟氧化物层，用较薄的栅极电介质层代替低电压晶体管区域中的虚拟氧化物，并将用于DEMOS的栅极电介质的虚拟氧化物 或LDMOS晶体管。 一种形成集成电路的工艺，包括形成用于离子注入低压和中压晶体管的虚拟氧化物层，用较薄的栅介质层代替低电压晶体管中的虚拟氧化物，用中间电压晶体管替代中间电压晶体管中的虚拟氧化物， 另一栅极电介质层，并且保留用于DEMOS或LDMOS晶体管的栅极电介质的虚拟氧化物。

公开(公告)号：US08426281B2

公开(公告)日：2013-04-23

申请号：US12961885

申请日：2010-12-07

申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L21/336

CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device 100 comprising source and drain regions 105, 107, and insulating region 115 and a plate structure 140. The source and drain regions are on or in a semiconductor substrate 110. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer 120 and a thick layer 122. The thick layer includes a plurality of insulating stripes 132 that are separated from each other and that extend across a length 135 between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands 143 that are directly over individual ones of the plurality of insulating stripes.

摘要翻译： 包括源极和漏极区域105,107以及绝缘区域115和板状结构140的半导体器件100.源极和漏极区域在半导体衬底110上或半导体衬底110中。绝缘区域在半导体衬底上或半导体衬底中并且位于 源极和漏极区域。 绝缘区域具有薄层120和厚层122.厚层包括彼此分离并且跨越源极和漏极区域之间的长度135延伸的多个绝缘条132。 板结构位于源极和漏极区之间，其中板结构位于薄层上，厚层的部分，板结构具有一个或多个导电带143，其直接位于多个 绝缘条纹

公开(公告)号：US08253193B2

公开(公告)日：2012-08-28

申请号：US13006566

申请日：2011-01-14

申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

IPC分类号： H01L29/66

CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

公开(公告)号：US20120112277A1

公开(公告)日：2012-05-10

申请号：US13284011

申请日：2011-10-28

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L21/265 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

摘要翻译： 一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。 下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。 一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。 一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

公开(公告)号：US20090294841A1

公开(公告)日：2009-12-03

申请号：US12509922

申请日：2009-07-27

申请人： Sameer Pendharkar ,  Binghua Hu

发明人： Sameer Pendharkar ,  Binghua Hu

IPC分类号： H01L29/78

CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

摘要翻译： 一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。 此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。 此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％ 身体区域。 此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。