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52 条记录 (耗时 0.036 秒)

    Measuring circuit and reading method for memory cells
    31.
    发明申请
    Measuring circuit and reading method for memory cells 失效
    记忆单元的测量电路和读取方法

    公开(公告)号：US20070086240A1

    公开(公告)日：2007-04-19

    申请号：US11542755

    申请日：2006-10-04

    申请人： Thomas Kern ,  Thomas Mikolajick ,  Jan-Malte Schley

    发明人： Thomas Kern ,  Thomas Mikolajick ,  Jan-Malte Schley

    IPC分类号： G11C16/04

    CPC分类号： G11C16/26 ,  G11C16/0475

    摘要： An electronic circuit arrangement includes at least one memory element in which at least two electrical quantities can be stored. A switching unit is electrically connected to the memory element and has at least one first circuit path and a second circuit path. A storage unit has a first partial storage unit and a second partial storage unit. Each partial storage unit is set up for storing at least one electrical quantity. The switching unit is set up in such a way that it can sequentially pass a first one of the at least two electrical quantities along the first circuit path to the first partial storage unit and a second one of the at least two electrical quantities along the second circuit path to the second partial storage unit.

    摘要翻译： 电子电路装置包括至少一个可存储至少两个电量的存储元件。 开关单元电连接到存储元件并且具有至少一个第一电路路径和第二电路路径。 存储单元具有第一部分存储单元和第二部分存储单元。 每个部分存储单元设置用于存储至少一个电量。 开关单元被设置成使得其可以顺序地将沿着第一电路路径的至少两个电量中的第一个顺序地传递到第一部分存储单元，并且沿着第二电路顺序地通过至少两个电量中的第二个 到第二部分存储单元的电路路径。

    Measuring circuit and reading method for memory cells
    32.
    发明授权
    Measuring circuit and reading method for memory cells 失效
    记忆单元的测量电路和读取方法

    公开(公告)号：US07646647B2

    公开(公告)日：2010-01-12

    申请号：US11542755

    申请日：2006-10-04

    申请人： Thomas Kern ,  Thomas Mikolajick ,  Jan-Malte Schley

    发明人： Thomas Kern ,  Thomas Mikolajick ,  Jan-Malte Schley

    IPC分类号： G11C11/03

    CPC分类号： G11C16/26 ,  G11C16/0475

    摘要： An electronic circuit arrangement includes at least one memory element in which at least two electrical quantities can be stored. A switching unit is electrically connected to the memory element and has at least one first circuit path and a second circuit path. A storage unit has a first partial storage unit and a second partial storage unit. Each partial storage unit is set up for storing at least one electrical quantity. The switching unit is set up in such a way that it can sequentially pass a first one of the at least two electrical quantities along the first circuit path to the first partial storage unit and a second one of the at least two electrical quantities along the second circuit path to the second partial storage unit.

    摘要翻译： 电子电路装置包括至少一个可存储至少两个电量的存储元件。 开关单元电连接到存储元件并且具有至少一个第一电路路径和第二电路路径。 存储单元具有第一部分存储单元和第二部分存储单元。 每个部分存储单元设置用于存储至少一个电量。 开关单元被设置成使得其可以顺序地将沿着第一电路路径的至少两个电量中的第一个顺序地传递到第一部分存储单元，并且沿着第二电路顺序地通过至少两个电量中的第二个 到第二部分存储单元的电路路径。

    Evaluation circuit and evaluation method for the assessment of memory cell states
    33.
    发明授权
    Evaluation circuit and evaluation method for the assessment of memory cell states 失效
    用于评估存储单元状态的评估电路和评估方法

    公开(公告)号：US07616492B2

    公开(公告)日：2009-11-10

    申请号：US11543306

    申请日：2006-10-04

    申请人： Thomas Kern ,  Thomas Mikolajick ,  Jan-Malte Schley

    发明人： Thomas Kern ,  Thomas Mikolajick ,  Jan-Malte Schley

    IPC分类号： G11C11/34

    CPC分类号： G11C11/5642 ,  G11C11/5671 ,  G11C16/0475 ,  G11C27/005

    摘要： An electronic circuit arrangement includes a storage unit set up for storing at least two analog electrical quantities. A first evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses the at least two analog electrical quantities and provides a first assessment result. A second evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses at least one of the at least two analog electrical quantities with a predetermined threshold value and provides a second assessment result.

    摘要翻译： 电子电路装置包括设置用于存储至少两个模拟电量的存储单元。 第一评估电路耦合到存储单元并且被设置成使得其评估至少两个模拟电量并提供第一评估结果。 第二评估电路耦合到存储单元并且被设置成使得其以预定阈值评估至少两个模拟电量中的至少一个并提供第二评估结果。

    Method for fabricating a semiconductor memory cell
    35.
    发明申请
    Method for fabricating a semiconductor memory cell 失效
    半导体存储单元的制造方法

    公开(公告)号：US20050141271A1

    公开(公告)日：2005-06-30

    申请号：US11021626

    申请日：2004-12-22

    申请人： Thomas Mikolajick

    发明人： Thomas Mikolajick

    IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L21/28273 ,  G11C16/0475 ,  H01L29/7887 ,  H01L29/7923

    摘要： In order to be able to store information in a non-volatile fashion as compactly and as flexibly as possible in a semiconductor memory cell, the original gate region of a conventional memory transistor is removed, and a memory gate configuration having a plurality of memory gates that are spatially separate from one another and that are electrically insulated with respect to one another is formed.

    摘要翻译： 为了能够在半导体存储单元中尽可能紧凑地且尽可能地灵活地存储非易失性的信息，去除了常规存储晶体管的原始栅极区域，并且具有多个存储器栅极的存储器栅极配置 在空间上彼此分离并且彼此相互电绝缘。

    Charge trapping memory cell, method for fabricating it, and semiconductor memory device
    36.
    发明授权
    Charge trapping memory cell, method for fabricating it, and semiconductor memory device 失效
    电荷捕获存储单元，其制造方法和半导体存储器件

    公开(公告)号：US06891751B2

    公开(公告)日：2005-05-10

    申请号：US10283857

    申请日：2002-10-30

    申请人： Thomas Mikolajick

    发明人： Thomas Mikolajick

    IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L29/792

    CPC分类号： H01L21/28282 ,  G11C16/0475 ,  H01L29/7923

    摘要： For particularly flexible and space-saving information storage, a charge trapping memory cell and a corresponding semiconductor memory device include a charge trapping gate configuration provided with a plurality of charge trapping gates each configured for substantially independent information storage. As a result, a plurality of information units can be stored independently of one another in the memory cell. Also provided is a method for producing such a memory cell.

    摘要翻译： 对于特别灵活和节省空间的信息存储，电荷俘获存储器单元和相应的半导体存储器件包括电荷俘获门配置，其配置有多个电荷俘获门，每个电荷俘获门被配置为基本上独立的信息存储。 结果，可以在存储单元中彼此独立地存储多个信息单元。 还提供了一种用于制造这种存储单元的方法。

    Method for producing ferroelectric capacitors and integrated semiconductor memory chips
    37.
    发明授权
    Method for producing ferroelectric capacitors and integrated semiconductor memory chips 失效
    铁电电容器和集成半导体存储器芯片的制造方法

    公开(公告)号：US06875652B2

    公开(公告)日：2005-04-05

    申请号：US10638594

    申请日：2003-08-11

    申请人： Igor Kasko ,  Matthias Kroenke ,  Thomas Mikolajick

    发明人： Igor Kasko ,  Matthias Kroenke ,  Thomas Mikolajick

    IPC分类号： H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/8244

    CPC分类号： H01L21/7687 ,  H01L21/76888 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

    摘要： The invention relates to a method for producing ferroelectric capacitors that are structured using the stack principle and that are used in integrated semiconductor memory chips. The individual capacitor modules have an oxygen barrier between a lower capacitor electrode and an electrically conductive plug. At a site where it is not covered by the corresponding oxygen barrier, an unstructured adhesive layer is oxidized by the oxygen arising during the tempering process of the ferroelectric and forms insulating segments at the site in such a way that the lower capacitor electrodes of the ferroelectric capacitors are electrically insulated from one another. This makes it possible to dispense with structuring the adhesive layer. Furthermore, the layer serves as a getter of oxygen and inhibits the diffusion of oxygen to the plug.

    摘要翻译： 本发明涉及一种用于制造铁电电容器的方法，所述铁电电容器使用堆叠原理构造并且用于集成半导体存储器芯片。 各个电容器模块在下部电容器电极和导电插塞之间具有氧气阻挡层。 在不被相应氧气阻挡层覆盖的位置处，非结构化粘合剂层被铁电体的回火过程中产生的氧氧化，并且在现场形成绝缘段，使得铁电体的下电容器电极 电容器彼此电绝缘。 这使得可以省略结构化粘合剂层。 此外，该层用作氧气的吸气剂并且抑制氧扩散到塞子。

    Method for fabricating a memory cell
    38.
    发明授权
    Method for fabricating a memory cell 失效
    用于制造存储单元的方法

    公开(公告)号：US07192830B2

    公开(公告)日：2007-03-20

    申请号：US10862818

    申请日：2004-06-07

    申请人： Matthias Goldbach ,  Thomas Mikolajick ,  Albert Birner

    发明人： Matthias Goldbach ,  Thomas Mikolajick ,  Albert Birner

    IPC分类号： H01L21/336

    CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7887

    摘要： Silicon nanocrystals are applied as storage layer (6) and removed using spacer elements (11) laterally with respect to the gate electrode (5). By means of an implantation of dopant, source/drain regions (2) are fabricated in a self-aligned manner with respect to the storage layer (6). The portions of the storage layer (6) are interrupted by the gate electrode (5) and the gate dielectric (4), so that a central portion of the channel region (3) is not covered by the storage layer (6). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.

    摘要翻译： 将硅纳米晶体作为存储层（6）施加，并且使用间隔元件（11）相对于栅电极（5）横向去除。 通过掺杂剂的注入，源极/漏极区域（2）以相对于存储层（6）的自对准方式制造。 存储层（6）的部分被栅极（5）和栅极电介质（4）中断，使得沟道区域（3）的中心部分不被存储层（6）覆盖。 该存储单元适合作为虚拟地面架构中的多位闪存单元。