公开(公告)号：US08822967B2

公开(公告)日：2014-09-02

申请号：US13433039

申请日：2012-03-28

申请人： Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derhacobian ,  Vei-Han Chan

发明人： Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derhacobian ,  Vei-Han Chan

IPC分类号： H01L45/00 ,  H03K19/02 ,  G11C13/00

CPC分类号： H01L45/1226 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1683 ,  H03K19/02

摘要： Phase change devices, particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. Structure allows application in which an electrical connection can be created between two active terminals, with control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals, allowing use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. Programming control can be placed outside of main signal path through the phase change device, reducing impact of associated capacitance and resistance of the device.

摘要翻译： 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其中导电性可以根据施加到控制电极的控制信号进行修改。 结构允许应用，其中可以在两个活动终端之间产生电连接，并且使用单独的终端或终端来实现连接的控制。 因此，可以独立于两个有源端子之间的路径的电阻增加加热器元件的电阻，允许使用较小的加热器元件，从而需要更少的电流以产生每单位面积相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

公开(公告)号：US08486745B2

公开(公告)日：2013-07-16

申请号：US11811077

申请日：2007-06-07

申请人： Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derharcobian ,  Vei-Han Chan

发明人： Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derharcobian ,  Vei-Han Chan

IPC分类号： H01L45/00

CPC分类号： H01L45/1226 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1683 ,  H03K19/02

摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.

摘要翻译： 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其中导电性可以根据施加到控制电极的控制信号进行修改。 这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。 因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。 这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

公开(公告)号：US08178380B2

公开(公告)日：2012-05-15

申请号：US12459917

申请日：2009-07-09

申请人： Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derharcobian ,  Vei-Han Chan

发明人： Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derharcobian ,  Vei-Han Chan

IPC分类号： H01L45/00

CPC分类号： H01L45/1226 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1683 ,  H03K19/02

摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.

摘要翻译： 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其中导电性可以根据施加到控制电极的控制信号进行修改。 这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。 因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。 这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

公开(公告)号：US07511532B2

公开(公告)日：2009-03-31

申请号：US11267718

申请日：2005-11-03

申请人： Narbeh Derharcobian ,  Louis Charles Kordus, II ,  Colin Neal Murphy ,  Antonietta Oliva ,  Vei-Han Chan ,  Thomas Stewart, Jr.

发明人： Narbeh Derharcobian ,  Louis Charles Kordus, II ,  Colin Neal Murphy ,  Antonietta Oliva ,  Vei-Han Chan ,  Thomas Stewart, Jr.

IPC分类号： H03K19/177 ,  G11C11/34

CPC分类号： G11C13/0011 ,  B82Y10/00 ,  G11C13/0004 ,  G11C13/025 ,  G11C23/00 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778

摘要： Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.

摘要翻译： 可重构的电子结构和电路使用可编程的非易失性存储元件。 可编程的非易失性存储器元件可以执行存储和/或开关的功能，以产生诸如交叉开关，多路复用器，查找表（LUT）和在可编程逻辑结构（例如，（FPGA））中使用的其它逻辑电路的组件， ）。 可编程的非易失性存储元件包括基于相变存储器，可编程金属化，碳纳米机电（CNT-NEM）或金属纳米机电器件技术的一个或多个结构。

公开(公告)号：US06989319B1

公开(公告)日：2006-01-24

申请号：US10718707

申请日：2003-11-24

申请人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

发明人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21/265

CPC分类号： H01L21/265 ,  H01L21/28176 ,  H01L21/28273

摘要： Methods and arrangements are provided for significantly reducing electron trapping in semiconductor devices having a polysilicon feature and an overlying dielectric layer. The methods and arrangements employ a nitrogen-rich region within the polysilicon feature near the interface to the overlying dielectric layer. The methods include selectively implanting nitrogen ions through at least a portion of the overlying dielectric layer and into the polysilicon feature to form an initial nitrogen concentration profile within the polysilicon feature. Next, the temperature within the polysilicon feature is raised to an adequately high temperature, for example using rapid thermal anneal (RTA) techniques, which cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards either the interface with the overlying dielectric layer or the interface with an underlying layer. Consequently, the polysilicon feature has a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The migration of nitrogen further forms a contiguous reduced-nitrogen region located between the first nitrogen-rich region and the second nitrogen-rich region. The contiguous reduced-nitrogen region has a lower concentration of nitrogen than does the first nitrogen-rich region and the second nitrogen-rich region. The first nitrogen-rich region has been found to reduce electron trapping within the polysilicon feature. Thus, for example, in a non-volatile memory device wherein the polysilicon feature is a floating gate, false programming of the memory device can be significantly avoided by reducing the number of trapped electrons in the floating gate.

摘要翻译： 提供了用于显着减少具有多晶硅特征和上覆电介质层的半导体器件中的电子俘获的方法和装置。 所述方法和装置在靠近覆盖的介电层的界面附近使用多晶硅特征内的富氮区域。 所述方法包括通过至少部分上覆介质层选择性地注入氮离子并进入多晶硅特征以在多晶硅特征内形成初始氮浓度分布。 接下来，将多晶硅特征中的温度升高到足够高的温度，例如使用快速热退火（RTA）技术，其使得初始氮浓度分布由于大部分氮朝着界面迁移而改变 与上层电介质层或与下层的界面。 因此，多晶硅特征具有在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域。 氮的迁移进一步形成位于第一富氮区和第二富氮区之间的连续的还原氮区。 连续的还原氮区域具有比第一富氮区域和第二富氮区域低的氮浓度。 已发现第一富氮区域减少多晶硅特征内的电子俘获。 因此，例如，在其中多晶硅特征是浮动栅极的非易失性存储器件中，可以通过减少浮置栅极中的俘获电子的数量来显着地避免存储器件的伪编程。

公开(公告)号：US06821847B2

公开(公告)日：2004-11-23

申请号：US09969841

申请日：2001-10-02

申请人： Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

发明人： Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

公开(公告)号：US06815760B2

公开(公告)日：2004-11-09

申请号：US10200443

申请日：2002-07-22

申请人： Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

发明人： Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

公开(公告)号：US06570215B2

公开(公告)日：2003-05-27

申请号：US10199157

申请日：2002-07-18

申请人： Hsing T. Tuan ,  Vei-Han Chan ,  Chung Wai Leung ,  Chia-Shun Hsiao

发明人： Hsing T. Tuan ,  Vei-Han Chan ,  Chung Wai Leung ,  Chia-Shun Hsiao

IPC分类号： H01L2362

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42336

摘要： In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

公开(公告)号：US06275415B1

公开(公告)日：2001-08-14

申请号：US09416563

申请日：1999-10-12

申请人： Sameer S. Haddad ,  Ravi S. Sunkavalli ,  Wing Han Leung ,  John Chen ,  Ravi Prakash Gutala ,  Colin Bill ,  Vei-Han Chan

发明人： Sameer S. Haddad ,  Ravi S. Sunkavalli ,  Wing Han Leung ,  John Chen ,  Ravi Prakash Gutala ,  Colin Bill ,  Vei-Han Chan

IPC分类号： G11C1604

CPC分类号： G11C16/12

摘要： A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated. In another embodiment, a bias voltage is applied to the common source terminal and a bias voltage is applied to the common well voltage. The combination of the voltages applied to the control gates and to the sources decreases loading on the bitlines to ensure that VDS does not fall below a required level necessary for the maintenance of the hot carrier effect during programming. A bias voltage can also be applied to the wells of the memory cells while the common source terminal is held at ground. Feedback control of the programming gate voltages can be used to control the power required for programming.

摘要翻译： 一种具有多个存储单元的存储器件，每个存储体具有多个存储器单元，以及一种编程器件中的多个存储器单元的方法，其中偏置电压施加到多个存储器单元的公共源极端子，并且将时变电压施加到 要编程的存储单元。 在一个实施例中，施加到要编程的存储器单元的栅极的电压是斜坡电压。 在第二实施例中，施加到待编程的存储器单元的栅极的电压是增加的阶梯电压。 在另一个实施例中，选择施加到公共源极端子的偏置电压和施加到要编程的存储器单元的控制栅极的电压，使得流过被编程的单元的电流减小，并且来自存储器单元的泄漏电流 不被编程的基本上被消除。 在另一个实施例中，将偏置电压施加到公共源极端子，并将偏置电压施加到公共井电压。 施加到控制栅极和源极的电压的组合减少了位线上的负载，以确保VDS不会降低到在编程期间维持热载流子效应所需的水平。 偏置电压也可以施加到存储单元的阱，同时公共源极保持在地。 编程栅极电压的反馈控制可用于控制编程所需的功率。

公开(公告)号：US06258668B1

公开(公告)日：2001-07-10

申请号：US09487501

申请日：2000-01-19

申请人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

发明人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0491 ,  H01L27/115

摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

摘要翻译： 在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。 单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。 位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。 由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。 使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。 通过使用Fowler-Nordheim从浮置栅极到控制栅极的隧道，通过在浮栅的壁上形成的多晶硅氧化物来消除电池。