摘要:
A method of forming a flash memory cell is disclosed where nitrogen treatment or implantation is employed. Nitrogen introduced into the upper layers of the polysilicon of the floating gate is instrumental in forming an unusually thin layer comprising nitrogen-oxygen-silicon. This N--O--Si layer is formed while growing the bottom oxide layer of the oxide-nitride-oxide, or ONO, the intergate layer between the floating gate and the control gate of the flash memory cell. Nitrogen in the first polysilicon layer provides control for the thickness of the bottom oxide while at the same time suppressing the gradual gate oxidation (GGO) effect in the floating gate. The now augmented ONO composite through the N--O--Si layer provides an enhanced intergate dielectric and hence, a flash memory cell with more precise coupling ratio and better performance.
摘要:
The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
摘要:
A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.
摘要:
A fully logic process compatible non-volatile memory cell has a well on a substrate, a pair of source and drain outside the well, a channel between the source and drain, a control gate in the well, and a floating gate having a first portion above the channel, and a second portion above the well. The control gate includes two regions having opposite conductivity types and a third region between the two regions and under the second portion of the floating gate, and thus eliminates the parasitic depletion capacitor in the coupling path of the cell, thereby improving the coupling ratio.
摘要:
A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.
摘要:
The present invention discloses a level shift circuit which comprises: level shift means for receiving an input of a first operational voltage and generating an output of a second operational voltage; and a current path connecting with a source of the second operational voltage and providing current to the output of the level shift means to speed up output level switching. The circuit preferably further comprises a power consumption control circuit for stopping excess power consumption when the output of the level shift means has substantially accomplished level switching.
摘要:
A plurality of switches, an inductor and two capacitors are configured to be a boost-inverting converter. To operate the converter in a boost-inverting mode, a control apparatus and method switch the switches such that the inductor is energized in a first phase, the first capacitor is discharged to produce an inverting voltage in a second phase, and the capacitor Cout1 is discharged to produce the inverting voltage and the second capacitor is charged to produce a boost voltage in a third phase. Therefore, the boost-inverting converter has lower peak inductor current and less power loss, and the limitation to the switch design for the boost-inverting converter is relaxed.
摘要:
A method, which is for determining switching state of a transistor-based switching device that includes a set of transistors, includes the steps of: applying a bias voltage to a transistor having a fastest response so as to dispose the transistors in the set in a desired transistor state; detecting a voltage level at a transistor having a slowest response to the bias voltage; and comparing the detected voltage level with a predetermined threshold voltage level in order to determine the switching state of the switching device. A transistor-based switching device is also disclosed.
摘要:
In a LED driver using a depletion mode transistor to serve as a current source, the depletion mode transistor is self-biased for providing a driving current to drive at least one LED, thereby requesting no additional control circuit to control the depletion mode transistor. The driving current is independent on the supply voltage coupled to the at least one LED, thereby requesting no additional voltage regulator, reducing the circuit size, and lowering the cost.
摘要:
A new process is provided whereby LDD regions for HV CMOS devices and for LV CMOS devices are created using one processing sequence. The gate electrodes for both the High Voltage and the Low Voltage devices are created on the surface of a silicon substrate. The High Voltage LDD (HVLDD) is performed self-aligned with the HV CMOS gate electrode, a gate anneal is performed for both the HV and the LV CMOS devices. The Low Voltage LDD (LVLDD) is performed self-aligned with the LV CMOS gate electrodes. The gate electrodes of the CMOS devices are after this completed with the formation of the gate spacers, the source/drain implants and the back-end processing that is required for CMOS devices.