公开(公告)号：US08367509B1

公开(公告)日：2013-02-05

申请号：US13239030

申请日：2011-09-21

申请人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/76897

摘要： A method for forming a contact of a semiconductor device with reduced step height is disclosed, comprising forming a plurality of gates, forming a buffer layer on each of the gates, forming an insulating layer to fill spaces between the gates, forming strip-shaped photoresist patterns which cross the gates, etching the insulating layer to form first openings using a self-aligning process with the gates and the strip-shaped photoresist patterns as a mask, forming a conductive contact layer to fill the first openings, performing a first chemical mechanical polish (CMP) process to the conductive contact layer, removing the buffer layer, and forming a second chemical mechanical polish (CMP) process to the conductive contact layer.

摘要翻译： 公开了一种用于形成具有降低的台阶高度的半导体器件的接触的方法，包括形成多个栅极，在每个栅极上形成缓冲层，形成绝缘层以填充栅极之间的空间，形成带状光致抗蚀剂 通过栅极和带状光致抗蚀剂图案作为掩模蚀刻绝缘层以形成第一开口，形成导电接触层以填充第一开口，执行第一化学机械 抛光（CMP）工艺到导电接触层，去除缓冲层，以及对导电接触层形成第二化学机械抛光（CMP）工艺。

公开(公告)号：US20120302030A1

公开(公告)日：2012-11-29

申请号：US13118451

申请日：2011-05-29

申请人： Hsiu-Chun Lee ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Hsiu-Chun Lee ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/02 ,  H01L21/28

CPC分类号： H01L29/66181 ,  H01L29/945

摘要： A method of fabricating a deep trench capacitor includes the steps as follows. Firstly, a substrate having a trench therein is provided. Then, a bottom electrode is formed in the substrate around the trench. Later, a capacitor dielectric layer is formed to surround an inner sidewall of the trench. After that, a first conductive layer is form to fill up the trench. Subsequently, a material layer is formed on the substrate. Later, a hole is formed in the material layer, wherein the hole is directly above the trench. Finally, a second conductive layer is form to fill in the hole.

摘要翻译： 制造深沟槽电容器的方法包括以下步骤。 首先，提供其中具有沟槽的衬底。 然后，在沟槽周围的衬底中形成底部电极。 之后，形成电容器电介质层以包围沟槽的内侧壁。 之后，形成填充沟槽的第一导电层。 接着，在基板上形成材料层。 之后，在该材料层中形成一个孔，其中孔直接在沟槽的上方。 最后，第二导电层是填充孔的形式。

公开(公告)号：US20120301833A1

公开(公告)日：2012-11-29

申请号：US13118447

申请日：2011-05-29

申请人： Hsiu-Chun Lee ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Hsiu-Chun Lee ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： G03F7/20

CPC分类号： H01L21/3083

摘要： The present invention provides a method of reducing microloading effect by using a photoresist layer as a buffer. The method includes: providing a substrate defined with a dense region and an isolated region. Then, a dense feature pattern and an isolated feature pattern are formed on the dense region and the isolated region respectively. After that, a photoresist layer is formed to cover the isolated region. Finally, the substrate and the photoresist layer are etched by taking the dense feature pattern and the isolated feature pattern as a mask.

摘要翻译： 本发明提供一种通过使用光致抗蚀剂层作为缓冲液来减少微载物效应的方法。 该方法包括：提供限定有致密区域和隔离区域的衬底。 然后，分别在密集区域和孤立区域上形成致密特征图案和隔离特征图案。 之后，形成光致抗蚀剂层以覆盖隔离区域。 最后，通过将密集特征图案和孤立的特征图案作为掩模来蚀刻基底和光致抗蚀剂层。

公开(公告)号：US20120289048A1

公开(公告)日：2012-11-15

申请号：US13104986

申请日：2011-05-11

申请人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/306 ,  H01L21/304

CPC分类号： H01L27/0203 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.

摘要翻译： 一种用于获得现有集成电路的布局设计的方法，其中集成电路管芯以倾斜角抛光以形成倾斜的抛光表面，并且获得倾斜抛光表面的一个或多个图像。 图像可以直接重叠，或者图像或图像可以用于提供信息以获得包括布局结构的至少一个重复单元结构的布局设计。

公开(公告)号：US20120288802A1

公开(公告)日：2012-11-15

申请号：US13103108

申请日：2011-05-09

申请人： Chang-Ming Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chang-Ming Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： G03F7/20

CPC分类号： H01L21/32139 ,  H01L21/28123 ,  H01L21/28132

摘要： A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.

摘要翻译： 一种形成栅极导体结构的方法。 提供了具有栅电极层的基板。 形成覆盖栅电极层的多层硬掩模。 多层硬掩模包括第一硬掩模，第二硬掩模和第三硬掩模。 在多层硬掩模上形成光刻胶图形。 执行第一蚀刻工艺以蚀刻第三硬掩模，使用光致抗蚀剂图案作为第一蚀刻抗蚀剂，由此形成图案化的第三硬掩模。 执行第二蚀刻工艺以蚀刻第二硬掩模和第一硬掩模，使用图案化的第三硬掩模作为第二蚀刻抗蚀剂，由此形成图案化的第一硬掩模。 执行第三蚀刻工艺以蚀刻栅极电极层的层，使用图案化的第一硬掩模作为第三蚀刻抗蚀剂。

公开(公告)号：US20120286819A1

公开(公告)日：2012-11-15

申请号：US13105913

申请日：2011-05-12

申请人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： G01R31/26 ,  H01L21/28 ,  H01L23/48

CPC分类号： H01L22/34 ,  G01R31/02 ,  G01R31/26 ,  G01R31/2644 ,  G01R31/2831

摘要： A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.

摘要翻译： 公开了MOS测试结构。 划线区域设置在具有与第一侧相对的第一侧和第二侧的基板上。 外延层设置在第一侧上，掺杂阱设置在外延层上，并且掺杂区域设置在掺杂阱上。 第一深度的沟槽栅极设置在掺杂区域，掺杂阱和划线区域中。 导电材料填充测试，通过该测试具有覆盖测试通孔的内壁的第二深度和隔离，并且设置在掺杂区域，掺杂阱，外延层和划线区域中，以电连接 到外延层，使得测试通孔能够一起测试外延层和衬底。

公开(公告)号：US20120270474A1

公开(公告)日：2012-10-25

申请号：US13090284

申请日：2011-04-20

申请人： Chien-Mao Liao ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chien-Mao Liao ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B24B49/00

CPC分类号： B24B37/34 ,  B24B49/00

摘要： A polishing pad wear detecting apparatus suitable for a chemical mechanical polishing (CMP) apparatus is provided. The polishing pad wear detecting apparatus includes an arm and a height detector. One end of the arm is fastened on the CMP apparatus. The height detector is disposed on the arm for detecting height variation of a polishing pad.

摘要翻译： 提供了适用于化学机械抛光（CMP）装置的抛光垫磨损检测装置。 抛光垫磨损检测装置包括臂和高度检测器。 臂的一端固定在CMP装置上。 高度检测器设置在臂上用于检测抛光垫的高度变化。

公开(公告)号：US20120270411A1

公开(公告)日：2012-10-25

申请号：US13092994

申请日：2011-04-25

申请人： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/316

CPC分类号： H01L21/28229 ,  H01L29/518

摘要： A manufacturing method of a gate dielectric layer is provided. An oxidation treatment is performed to form an oxide layer on a substrate. A nitridation treatment is performed to form a nitride layer on the oxide layer. An annealing treatment is performed in a mixing gas of N2 and O2, where the temperature of the annealing treatment is 900° C. to 950° C., the pressure of the annealing treatment is 5 Torr to 10 Torr, and the content ratio of the N2 to O2 is 0.5 to 0.8.

摘要翻译： 提供了栅介质层的制造方法。 进行氧化处理以在基板上形成氧化物层。 进行氮化处理以在氧化物层上形成氮化物层。 在N2和O2的混合气体中进行退火处理，其中退火处理的温度为900℃至950℃，退火处理的压力为5托至10托，并且含量比 N 2至O 2为0.5至0.8。

公开(公告)号：US20120256257A1

公开(公告)日：2012-10-11

申请号：US13081509

申请日：2011-04-07

申请人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/772

CPC分类号： H01L27/10879 ,  H01L27/10826 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/78

摘要： The present invention disclosed a recessed gate transistor with buried fins. The recessed gate transistor with buried fins is disposed in an active region on a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate, and sandwich the active region. A gate structure is disposed in the semiconductor substrate, wherein the gate structure includes: an upper part and a lower part. The upper part is disposed in the active region and a lower part having a front fin disposed in one of the two isolation regions, at least one middle fin disposed in the active region, and a last fin disposed in the other one of the two isolation regions, wherein the front fin are both elliptic cylindrical.

摘要翻译： 本发明公开了一种具有埋地鳍片的凹陷式栅极晶体管。 具有埋入散热片的嵌入式栅极晶体管设置在半导体衬底上的有源区中。 两个隔离区域设置在半导体衬底中并夹持有源区。 栅极结构设置在半导体衬底中，其中栅极结构包括：上部和下部。 上部设置在有源区域中，下部具有设置在两个隔离区域之一中的前翅片，设置在有源区域中的至少一个中间翅片，以及设置在两个隔离物中的另一个中的最后一个翅片 区域，其中前鳍都是椭圆柱形。

公开(公告)号：US20120256255A1

公开(公告)日：2012-10-11

申请号：US13081498

申请日：2011-04-07

申请人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66621

摘要： A recessed trench gate structure is provided. The recessed trench gate structure includes a substrate with a recessed trench, a gate dielectric layer disposed around an inner surface of the recessed trench, a lower gate conductor disposed at a lower portion of the recessed trench and on the gate dielectric layer. Specially, the lower gate conductor has a convex top surface. A spacer is disposed along an inner side wall of a upper portion of the recessed trench and a upper gate conductor is disposed on the lower gate conductor. The convex top surface can prevent the electric field from distributing not uniformly, so that the GIDL can be prevented.

摘要翻译： 提供凹槽沟槽栅结构。 所述凹槽沟槽栅极结构包括具有凹槽的衬底，设置在所述凹槽的内表面周围的栅极电介质层，设置在所述凹槽的下部和所述栅介质层上的下栅极导体。 特别地，下栅极导体具有凸起的顶表面。 间隔件沿着凹槽的上部的内侧壁设置，并且上栅极导体设置在下栅极导体上。 凸顶表面可以防止电场不均匀分布，从而可以防止GIDL。