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公开(公告)号：US20060286730A1
公开(公告)日：2006-12-21
申请号：US11154377
申请日：2005-06-15
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： A semiconductor structure and a method for forming the semiconductor structure are provided. The method for forming a semiconductor structure of the present invention may include the following steps. First, a substrate is provided, wherein a gate is formed over the substrate, and a plurality of offspacers are formed over a sidewall of the gate. Then, a source/drain trench is formed in the substrate at two sides of the gate respectively. Next, an outermost offspacer of the offspacers is removed to expose a flat surface on a surface of the substrate. Thereafter, the source/drain trenches are filled to form a source/drain region. Then, a lightly doped drain (LDD) region is formed in a portion of the substrate under the flat surface.
摘要翻译： 提供半导体结构和形成半导体结构的方法。 本发明的半导体结构的形成方法可以包括以下步骤。 首先，提供衬底，其中在衬底上形成栅极，并且在栅极的侧壁上方形成多个脱离层。 然后，在栅极的两侧分别在衬底中形成源极/漏极沟槽。 接下来，除去离子的最外层的隔离物以露出基底表面上的平坦表面。 此后，填充源极/漏极沟槽以形成源极/漏极区域。 然后，在平坦表面下的基板的一部分中形成轻掺杂漏极（LDD）区域。
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公开(公告)号：US20060099763A1
公开(公告)日：2006-05-11
申请号：US10904210
申请日：2004-10-28
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/265 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.
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公开(公告)号：US06974650B2
公开(公告)日：2005-12-13
申请号：US10063779
申请日：2002-05-12
申请人： Kay Ming Lee , Cheng-Wen Fan , Jiunn-Ren Hwang , Chih-Chiang Liu
发明人： Kay Ming Lee , Cheng-Wen Fan , Jiunn-Ren Hwang , Chih-Chiang Liu
CPC分类号： G03F1/36
摘要： A method of correcting a mask layout is provided. The mask layout includes a plurality of element patterns. An inspection program is executed to classify the element patterns of the mask layout into a plurality of element pattern types according to a pattern density of the element patterns. Following this, each of the element pattern types is corrected so as to prevent a plasma micro-loading effect.
摘要翻译： 提供了一种校正掩模布局的方法。 掩模布局包括多个元素图案。 执行检查程序，以根据元件图案的图案密度将掩模布局的元素图案分类为多个元素图案类型。 此后，校正每个元件图案类型以防止等离子体微负载效应。
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公开(公告)号：US06853031B2
公开(公告)日：2005-02-08
申请号：US10417167
申请日：2003-04-17
申请人： Wen-Shiang Liao , Jiunn-Ren Hwang , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Jiunn-Ren Hwang , Wei-Tsun Shiau
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66787 , H01L29/0657 , H01L29/1037 , H01L29/42376
摘要： A structure of a Trapezoid-Triple-Gate Field Effect Transistor (FET) includes a plurality of trapezoid pillars being transversely formed on an crystalline substrate or Silicon-On-Insulator (SOI) wafer. The trapezoid pillars can juxtapose with both ends connected each other. Each trapezoid pillar has a source, a channel region, and a drain aligned in longitudinal direction and a gate latitudinally superposes the channel region of the trapezoid pillar. The triple gate field effect transistor comprises a dielectric layer formed between the channel region and the conductive gate structure.
摘要翻译： 梯形三栅场效应晶体管（FET）的结构包括在晶体衬底或绝缘体上硅晶片上横向形成的多个梯形柱。 梯形柱可以并置，两端相互连接。 每个梯形柱具有在纵向方向上排列的源极，沟道区和漏极，栅极横向叠加梯形柱的沟道区域。 三栅场效应晶体管包括形成在沟道区和导电栅结构之间的电介质层。
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公开(公告)号：US06839126B2
公开(公告)日：2005-01-04
申请号：US10033891
申请日：2002-01-03
CPC分类号： G03F7/70141 , G03F7/70425 , G03F7/70466
摘要： A photolithography process with multiple exposures is provided. A photomask is placed and aligned above a wafer having a photoresist formed thereon at a predetermined distance. Multiple exposures are sequentially performed on the photoresist through the photomask. Each of the multiple exposures is provided with a respective illuminating setting that is optimized for one duty ratio of the photomask. Thereby, an optimum through-pitch performance for pattern transfer from the photomask unto the photoresist is obtained. Then, a development is performed on the photoresist.
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36.发明授权Optical proximity correction of pattern on photoresist through spacing of sub patterns 有权通过子图案的间隔对光致抗蚀剂上的图案进行光学邻近校正公开(公告)号：US06613485B2
公开(公告)日：2003-09-02
申请号：US10045432
申请日：2002-01-11
申请人： Jui-Tsen Huang , Jiunn-Ren Hwang
发明人： Jui-Tsen Huang , Jiunn-Ren Hwang
IPC分类号： G03F900
CPC分类号： G03F1/36 , Y10S430/143
摘要： An optical proximity correction method for rectifying pattern on photoresist. Line pattern of integrated circuit is divided into L-shape regions or T-shaped regions. The L-shaped or T-shaped regions are further dissected into rectangular patches. Area of each rectangular patch is suitably reduced and reproduced onto a photomask. The photomask is used to form a corrected photoresist pattern.
摘要翻译： 一种用于在光致抗蚀剂上整流图案的光学邻近校正方法。 集成电路的线路图案分为L形区域或T形区域。 L形或T形区域进一步分解成矩形斑块。 每个矩形贴片的面积被适当地减小并再现到光掩模上。 光掩模用于形成校正的光致抗蚀剂图案。
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公开(公告)号：US20060019451A1
公开(公告)日：2006-01-26
申请号：US10710581
申请日：2004-07-22
IPC分类号： H01L21/461
CPC分类号： H01L21/31116 , H01L21/31111 , H01L21/31122 , H01L21/823462 , H01L21/823481 , H01L29/517 , H01L29/78 , Y10S438/906
摘要： A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas plasma is provided to remove portions of the HfO2-containing gate dielectric.
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公开(公告)号：US06664028B2
公开(公告)日：2003-12-16
申请号：US09729575
申请日：2000-12-04
申请人： Jiunn-Ren Hwang , I-Hsiung Huang
发明人： Jiunn-Ren Hwang , I-Hsiung Huang
IPC分类号： G03C556
CPC分类号： G03F7/0035 , G03F7/40
摘要： A method of forming an opening in a wafer layer. At least two patterned photoresist layers are formed on a wafer layer. Using different photoresist layers, many openings are defined. The wafer layer is then etched to form the opening. Each photoresist layer has a parallel linear pattern such as parallel strips or an array of rectangular blocks. The photoresist layers are superposed in a way that spaces between the patterns for each photoresist layers overlapped with each other for form openings that expose the underlying wafer layers. The wafer layer exposed in the openings is then etched to form contact/via holes without rounded corners while the rounded profiles has been cancelled by the superposition of the photoresist layers.
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公开(公告)号：US06638664B2
公开(公告)日：2003-10-28
申请号：US09954933
申请日：2001-09-18
IPC分类号： G03F900
CPC分类号： G03F1/36
摘要： A method of correcting an optical mask pattern. A third pattern having a first strip-like pattern and a second strip-like pattern is provided. The first strip-like pattern attaches to the mid-section of the second strip-like pattern. A first modification step is conducted. A pair of assistant patterns is added to the respective sides of the first strip-like pattern to form a first modified pattern. A second modification step is conducted to shrink a portion of the first strip-like pattern to form a second modified pattern. Dimension in the reduced portion of the first strip-like pattern is a critical dimension of a main pattern. A third modification step is conducted using an optical proximity correction method. The second modified pattern is modified to a third modified pattern.
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公开(公告)号：US06380077B1
公开(公告)日：2002-04-30
申请号：US09835199
申请日：2001-04-13
申请人： I-Hsiung Huang , Jiunn-Ren Hwang
发明人： I-Hsiung Huang , Jiunn-Ren Hwang
IPC分类号： H01L214763
CPC分类号： H01L21/31144 , G03F7/0035 , H01L21/0271 , H01L21/76816
摘要： A method of forming a contact opening. A substrate having a conductive structure and a dielectric layer thereon is provided. A first photoresist layer is formed over the dielectric layer. A first photo-exposure followed by a photoresist development is conducted so that an opening pattern on the photomask is transferred to the first photoresist layer. The first photoresist layer includes a first opening that exposes a portion of the dielectric layer. A second photoresist layer is formed over the patterned first photoresist layer. The photomask is shifted horizontally relative to the substrate. A second photo-exposure followed by a photoresist development is conducted so that the opening pattern on the photomask is transferred to the second photoresist layer. The second photoresist layer includes a second opening that exposes a portion of the first photoresist layer and a portion of the first opening. Thereafter, using the first and the second photoresist layer as a mask, a portion of the dielectric layer is removed until a contact opening that exposes a portion of the conductive structure is formed. The first and the second photoresist layer are then removed, followed by forming a glue layer over the substrate to conform with a profile of the contact opening. Finally, the contact opening is filled with a metal plug.
摘要翻译： 一种形成接触开口的方法。 提供具有导电结构和其上的电介质层的衬底。 在电介质层上形成第一光致抗蚀剂层。 进行第一次曝光，然后进行光致抗蚀剂显影，使得光掩模上的开口图案被转印到第一光致抗蚀剂层。 第一光致抗蚀剂层包括暴露介电层的一部分的第一开口。 在图案化的第一光致抗蚀剂层上形成第二光致抗蚀剂层。 光掩模相对于基板水平移动。 进行第二次曝光，然后进行光致抗蚀剂显影，使得光掩模上的开口图案被转印到第二光致抗蚀剂层。 第二光致抗蚀剂层包括暴露第一光致抗蚀剂层的一部分和第一开口的一部分的第二开口。 此后，使用第一和第二光致抗蚀剂层作为掩模，去除电介质层的一部分，直到形成露出导电结构的一部分的接触开口。 然后去除第一和第二光致抗蚀剂层，随后在衬底上形成胶层以符合接触孔的轮廓。 最后，接触开口填充有金属塞。
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