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    Ternary content addressable memory and two-port static random access memory
    31.
    发明授权
    Ternary content addressable memory and two-port static random access memory 有权

    公开(公告)号：US11475952B2

    公开(公告)日：2022-10-18

    申请号：US17179418

    申请日：2021-02-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng ,  Chun-Chieh Chang

    IPC: G11C15/04

    Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

    Two-port ternary content addressable memory and layout pattern thereof, and associated memory device
    32.
    发明授权
    Two-port ternary content addressable memory and layout pattern thereof, and associated memory device 有权

    公开(公告)号：US10892013B2

    公开(公告)日：2021-01-12

    申请号：US16439680

    申请日：2019-06-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng

    IPC: G11C15/00 ,  G11C29/00 ,  G11C15/04 ,  H01L27/11 ,  H01L27/02 ,  G06F7/74

    Abstract: A two-port ternary content addressable memory (TCAM) and layout pattern thereof, and associated memory device are provided. The two-port TCAM may include a first storage unit, a second storage unit, a set of first search terminals, a set of second search terminals, a first comparison circuit, a second comparison circuit, a first match terminal and a second match terminal, wherein the first comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of first search terminals and the first match terminal, and the second comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of second search terminals and the second match terminal. First search data and second search data may be concurrently inputted into the two-port TCAM for determining whether the first search data and the second search data match content data within the two-port TCAM.

    Semiconductor structure
    37.
    发明授权
    Semiconductor structure 有权

    公开(公告)号：US09859282B1

    公开(公告)日：2018-01-02

    申请号：US15280333

    申请日：2016-09-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Shu-Ru Wang

    IPC: H01L27/108 ,  H01L29/78

    CPC classification number: H01L27/10805 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

    Abstract: A high-density semiconductor structure includes a substrate, a bit line and a first memory unit. The bit line, disposed on the substrate, has a first side and a second side. The first memory unit includes a first transistor, a first capacitor, a second transistor and a second capacitor. The first transistor disposed on the substrate has a first terminal and a second terminal. The first terminal connects the bit line. The first capacitor connects the second terminal of the first transistor. The second transistor disposed on the substrate has a third terminal and a fourth terminal. The third terminal connects the bit line. The second capacitor connects the fourth terminal of the second transistor. The first capacitor and the second capacitor are separated from the bit line in a direction perpendicular to an extending direction of the bit line and located on the first side of the bit line.

    Method for forming patterns
    39.
    发明授权
    Method for forming patterns 有权
    形成图案的方法

    公开(公告)号：US09316901B2

    公开(公告)日：2016-04-19

    申请号：US14259173

    申请日：2014-04-23

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Yu Chen ,  Chia-Wei Huang ,  Chun-Hsien Huang ,  Shih-Chun Tsai ,  Kai-Lin Chuang

    IPC: G03F9/00 ,  G03F1/36 ,  G03F1/70 ,  G03F1/68

    CPC classification number: G03F1/36 ,  G03F1/00 ,  G03F1/68 ,  G03F1/70

    Abstract: A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer.

    Abstract translation: 形成图案的方法包括以下步骤。 提供了包括第一目标图案和第一不可打印虚设图案的第一布局。 提供包括第二目标图案和第二可打印虚拟图案的第二布局，其中第二可打印虚拟图案的至少一部分与第一不可打印虚设图案曝光极限重叠，使得第二可打印虚设图案不能形成在晶片中。

    STRESS MEMORIZATION PROCESS AND SEMICONDUCTOR STRUCTURE INCLUDING CONTACT ETCH STOP LAYER
    40.
    发明申请
    STRESS MEMORIZATION PROCESS AND SEMICONDUCTOR STRUCTURE INCLUDING CONTACT ETCH STOP LAYER 审中-公开
    应力记忆过程和半导体结构，包括接触蚀刻停止层

    公开(公告)号：US20150228788A1

    公开(公告)日：2015-08-13

    申请号：US14179563

    申请日：2014-02-13

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Feng Chen ,  Wen-Yu Yang ,  Yu-Cheng Tung ,  Chun-Hsien Huang ,  Hui-Shen Shih ,  Shih-Chang Chang

    IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66

    CPC classification number: H01L29/7847 ,  H01L21/76832 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636

    Abstract: A stress memorization process including the following step is provided. A gate is formed on a substrate. A low-k dielectric layer with a dielectric constant lower than 3 is formed to entirely cover the gate and the substrate. A stress layer is formed to entirely cover the low-k dielectric layer. The stress layer and the low-k dielectric layer are removed. Moreover, a semiconductor structure including a contact etch stop layer is provided. A gate is disposed on a substrate. A porous layer entirely covers the gate and the substrate. A contact etch stop layer entirely covers the porous layer, wherein the thickness of the porous layer is thinner than the thickness of the contact etch stop layer.

    Abstract translation: 提供包括以下步骤的应力记忆过程。 栅极形成在基板上。 形成介电常数低于3的低k电介质层，以完全覆盖栅极和衬底。 形成应力层以完全覆盖低k电介质层。 去除应力层和低k电介质层。 此外，提供了包括接触蚀刻停止层的半导体结构。 栅极设置在基板上。 多孔层完全覆盖栅极和衬底。 接触蚀刻停止层完全覆盖多孔层，其中多孔层的厚度比接触蚀刻停止层的厚度薄。

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